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David E. Schimmel :
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Stephen P. DeWeerth , Girish N. Patel , Mario F. Simoni , David E. Schimmel , Ronald L. Calabrese A VLSI Architecture for Modeling Intersegmental Coordination. [Citation Graph (0, 0)][DBLP ] ARVLSI, 1997, pp:182-200 [Conf ] Christopher R. Clark , David E. Schimmel Scalable Pattern Matching for High Speed Networks. [Citation Graph (0, 0)][DBLP ] FCCM, 2004, pp:249-257 [Conf ] Marc Necker , Didier Contis , David E. Schimmel TCP-Stream Reassembly and State Tracking in Hardware. [Citation Graph (0, 0)][DBLP ] FCCM, 2002, pp:286-0 [Conf ] Christopher R. Clark , David E. Schimmel Modeling the data-dependent performance of pattern-matching architectures. [Citation Graph (0, 0)][DBLP ] FPGA, 2006, pp:73-82 [Conf ] Christopher R. Clark , David E. Schimmel Efficient Reconfigurable Logic Circuits for Matching Complex Network Intrusion Detection Patterns. [Citation Graph (0, 0)][DBLP ] FPL, 2003, pp:956-959 [Conf ] Vivek Garg , David E. Schimmel Architectural Support for Inter-Stream Communication in a MSIMD System. [Citation Graph (0, 0)][DBLP ] HPCA, 1995, pp:348-357 [Conf ] Chirag S. Patel , Sek M. Chai , Sudhakar Yalamanchili , David E. Schimmel Power Constrained Design of Multiprocessor Interconnection Networks. [Citation Graph (0, 0)][DBLP ] ICCD, 1997, pp:408-416 [Conf ] James D. Allen , David E. Schimmel The impact of pipelining on SIMD architectures. [Citation Graph (0, 0)][DBLP ] IPPS, 1995, pp:380-387 [Conf ] James D. Allen , David E. Schimmel Improving Memory Performance for Indirect Accesses on SIMD Computers. [Citation Graph (0, 0)][DBLP ] IPPS, 1996, pp:759-765 [Conf ] Vivek Garg , David E. Schimmel Hiding Communication Latency in Data Parallel Applications. [Citation Graph (0, 0)][DBLP ] IPPS/SPDP, 1998, pp:18-23 [Conf ] James D. Allen , Patrick T. Gaughan , David E. Schimmel , Sudhakar Yalamanchili Ariadne - An Adaptive Router for Fault-Tolerant Multicomputers. [Citation Graph (0, 0)][DBLP ] ISCA, 1994, pp:278-288 [Conf ] Bruce C. Kim , Abhijit Chatterjee , Madhavan Swaminathan , David E. Schimmel A Novel Low-Cost Approach to MCM Interconnect Test. [Citation Graph (0, 0)][DBLP ] ITC, 1995, pp:184-192 [Conf ] Paul J. Bond , Bruce C. Kim , Christopher A. Lee , David E. Schimmel A Methodology for Generation and Collection of Multiprocessor Traces. [Citation Graph (0, 0)][DBLP ] MASCOTS, 1994, pp:417-418 [Conf ] Hatem Sellami , James D. Allen , David E. Schimmel , Sudhakar Yalamanchili Simulation of Marked Graphs on SIMD Architectures Using Efficient Memory Management. [Citation Graph (0, 0)][DBLP ] MASCOTS, 1994, pp:343-348 [Conf ] Vivek Garg , David E. Schimmel CCSIMD: A Concurrent Communication and Computation Framework for SIMD Machines. [Citation Graph (0, 0)][DBLP ] PCRCW, 1997, pp:55-64 [Conf ] Chirag S. Patel , Sek M. Chai , Sudhakar Yalamanchili , David E. Schimmel Power/Performance Trade-offs for Direct Networks. [Citation Graph (0, 0)][DBLP ] PCRCW, 1997, pp:231-246 [Conf ] James D. Allen , Vivek Garg , David E. Schimmel Analysis of Control Parallelism in SIMD Instruction Streams. [Citation Graph (0, 0)][DBLP ] SPDP, 1993, pp:383-390 [Conf ] Vivek Garg , David E. Schimmel Performance modeling of dense Cholesky factorization on the MasPar MP-2. [Citation Graph (0, 0)][DBLP ] Concurrency - Practice and Experience, 1997, v:9, n:7, pp:697-719 [Journal ] David E. Schimmel , Chryssa Dislis Guest Editors' Introduction: Early Modeling and Analysis of Packaged Systems. [Citation Graph (0, 0)][DBLP ] IEEE Design & Test of Computers, 1998, v:15, n:3, pp:8-9 [Journal ] Joshua B. Fryman , Chad Huneycutt , Hsien-Hsin S. Lee , Kenneth M. Mackenzie , David E. Schimmel Energy-Efficient Network Memory for Ubiquitous Devices. [Citation Graph (0, 0)][DBLP ] IEEE Micro, 2003, v:23, n:5, pp:60-70 [Journal ] Patrick T. Gaughan , Binh Vien Dao , Sudhakar Yalamanchili , David E. Schimmel Distributed Deadlock-Free Routing in Faulty, Pipelined, Direct Interconnection Networks. [Citation Graph (0, 0)][DBLP ] IEEE Trans. Computers, 1996, v:45, n:6, pp:651-665 [Journal ] James D. Allen , David E. Schimmel Issues in the Design of High Performance SIMD Architectures. [Citation Graph (0, 0)][DBLP ] IEEE Trans. Parallel Distrib. Syst., 1996, v:7, n:8, pp:818-829 [Journal ] Girish N. Patel , Michael S. Reid , David E. Schimmel , Stephen P. DeWeerth An asynchronous architecture for modeling intersegmental neural communication. [Citation Graph (0, 0)][DBLP ] IEEE Trans. VLSI Syst., 2006, v:14, n:2, pp:97-110 [Journal ] Search in 0.002secs, Finished in 0.303secs