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Scott Little: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Chris Winstead, Jie Dai, Woo Jin Kim, Scott Little, Yong-Bin Kim, Chris J. Myers, Christian Schlegel
    Analog MAP Decoder for (8, 4) Hamming Code in Subthreshold CMOS. [Citation Graph (0, 0)][DBLP]
    ARVLSI, 2001, pp:132-147 [Conf]
  2. Scott Little, David Walter, Nicholas Seegmiller, Chris J. Myers, Tomohiro Yoneda
    Verification of Analog and Mixed-Signal Circuits Using Timed Hybrid Petri Nets. [Citation Graph (0, 0)][DBLP]
    ATVA, 2004, pp:426-440 [Conf]
  3. Martin Van De Bovenkamp, Ruben Jongkind, Gu Van Rhijn, Frans M. van Eijnatten, Gudela Grote, Jouni Lehtelä, Timo Leskinen, Peter Vink, Scott Little, Toni Wäfler
    The E/S Tool IT-Support for Ergonomic and Sociotechnical System Design. [Citation Graph (0, 0)][DBLP]
    ER (Workshops), 2001, pp:67-80 [Conf]
  4. Scott Little, Nicholas Seegmiller, David Walter, Chris J. Myers, Tomohiro Yoneda
    Verification of analog/mixed-signal circuits using labeled hybrid petri nets. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2006, pp:275-282 [Conf]
  5. Hao Zheng, Chris J. Myers, David Walter, Scott Little, Tomohiro Yoneda
    Verification of Timed Circuits with Failure Directed Abstractions. [Citation Graph (0, 0)][DBLP]
    ICCD, 2003, pp:28-35 [Conf]
  6. Chris J. Myers, Reid R. Harrison, David Walter, Nicholas Seegmiller, Scott Little
    The Case for Analog Circuit Verification. [Citation Graph (0, 0)][DBLP]
    Electr. Notes Theor. Comput. Sci., 2006, v:153, n:3, pp:53-63 [Journal]
  7. Hao Zheng, Chris J. Myers, David Walter, Scott Little, Tomohiro Yoneda
    Verification of timed circuits with failure-directed abstractions. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:3, pp:403-412 [Journal]
  8. Scott Little, David Walter, Kevin Jones, Chris Myers
    Analog/Mixed-Signal Circuit Verification Using Models Generated from Simulation Traces. [Citation Graph (0, 0)][DBLP]
    ATVA, 2007, pp:114-128 [Conf]
  9. David Walter, Scott Little, Chris Myers
    Bounded Model Checking of Analog and Mixed-Signal Circuits Using an SMT Solver. [Citation Graph (0, 0)][DBLP]
    ATVA, 2007, pp:66-81 [Conf]

  10. Symbolic Model Checking of Analog/Mixed-Signal Circuits. [Citation Graph (, )][DBLP]

  11. Application of Automated Model Generation Techniques to Analog/Mixed-Signal Circuits. [Citation Graph (, )][DBLP]

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