The SCEAS System
Navigation Menu

Search the dblp DataBase

Title:
Author:

Yong-Bin Kim: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Chris Winstead, Jie Dai, Woo Jin Kim, Scott Little, Yong-Bin Kim, Chris J. Myers, Christian Schlegel
    Analog MAP Decoder for (8, 4) Hamming Code in Subthreshold CMOS. [Citation Graph (0, 0)][DBLP]
    ARVLSI, 2001, pp:132-147 [Conf]
  2. T. Feng, Byoungjae Jin, J. Wang, Nohpill Park, Yong-Bin Kim, Fabrizio Lombardi
    Fault tolerant clockless wave pipeline design. [Citation Graph (0, 0)][DBLP]
    Conf. Computing Frontiers, 2004, pp:350-356 [Conf]
  3. Luca Schiano, Yong-Bin Kim, Fabrizio Lombardi
    Scan Test of IP Cores in an ATE Environment. [Citation Graph (0, 0)][DBLP]
    DELTA, 2004, pp:281-286 [Conf]
  4. Minsu Choi, Nohpill Park, Fabrizio Lombardi, Yong-Bin Kim, Vincenzo Piuri
    Balanced Redundancy Utilization in Embedded Memory Cores for Dependable Systems. [Citation Graph (0, 0)][DBLP]
    DFT, 2002, pp:419-427 [Conf]
  5. Kyung Ki Kim, Jing Huang, Yong-Bin Kim, Fabrizio Lombardi
    On the Modeling and Analysis of Jitter in ATE Using Matlab. [Citation Graph (0, 0)][DBLP]
    DFT, 2005, pp:285-293 [Conf]
  6. T. Feng, Nohpill Park, Yong-Bin Kim, Fabrizio Lombardi, Fred J. Meyer
    Reliability Modeling and Assurance of Clockless Wave Pipeline. [Citation Graph (0, 0)][DBLP]
    DFT, 2004, pp:442-450 [Conf]
  7. T. Feng, Nohpill Park, Yong-Bin Kim, Vincenzo Piuri
    Yield Modeling and Analysis of a Clockless Asynchronous Wave Pipeline with Pulse Faults. [Citation Graph (0, 0)][DBLP]
    DFT, 2003, pp:34-0 [Conf]
  8. Hamidreza Hashempour, Yong-Bin Kim, Nohpill Park
    A Test-Vector Generation Methodology for Crosstalk Noise Faults. [Citation Graph (0, 0)][DBLP]
    DFT, 2002, pp:40-50 [Conf]
  9. Kyung Ki Kim, Yong-Bin Kim, Fabrizio Lombardi
    Data Dependent Jitter (DDJ) Characterization Methodology. [Citation Graph (0, 0)][DBLP]
    DFT, 2005, pp:294-304 [Conf]
  10. Fengming Zhang, Young-Jun Lee, T. Kane, Luca Schiano, Mariam Momenzadeh, Yong-Bin Kim, Fred J. Meyer, Fabrizio Lombardi, S. Max, Phil Perkinson
    A Digital and Wide Power Bandwidth H-Field Generator for Automatic Test Equipment. [Citation Graph (0, 0)][DBLP]
    DFT, 2003, pp:159-166 [Conf]
  11. Fengming Zhang, Warren Necoechea, Peter Reiter, Yong-Bin Kim, Fabrizio Lombardi
    Load Board Designs Using Compound Dot Technique and Phase Detector for Hierarchical ATE Calibrations. [Citation Graph (0, 0)][DBLP]
    DFT, 2006, pp:486-494 [Conf]
  12. Yadunandana Yellambalase, Minsu Choi, Yong-Bin Kim
    Inherited Redundancy and Configurability Utilization for Repairing Nanowire Crossbars with Clustered Defects. [Citation Graph (0, 0)][DBLP]
    DFT, 2006, pp:98-106 [Conf]
  13. Byunghyun Jang, Yong-Bin Kim, Fabrizio Lombardi
    Error Tolerance of DNA Self-Assembly by Monomer Concentration Control. [Citation Graph (0, 0)][DBLP]
    DFT, 2006, pp:89-97 [Conf]
  14. Yeshwant Kolla, Yong-Bin Kim, John Carter
    A novel 32-bit scalable multiplier architecture. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2003, pp:241-244 [Conf]
  15. Rui Tang, Yong-Bin Kim
    PWAM signalling scheme for high speed serial link transceiver design. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2006, pp:49-52 [Conf]
  16. Rui Tang, Fengming Zhang, Yong-Bin Kim
    Quantum-dot cellular automata SPICE macro model. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2005, pp:108-111 [Conf]
  17. Fengming Zhang, Rui Tang, Yong-Bin Kim
    SET-based nano-circuit simulation and design method using HSPICE. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2004, pp:344-347 [Conf]
  18. Young-Jun Lee, Jihyun Lee, Yong-Bin Kim, Joseph Ayers, A. Volkovskii, Allen I. Selverston, Henry D. I. Abarbanel, Mikhail I. Rabinovich
    Low power real time electronic neuron VLSI design using subthreshold technique. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2004, pp:744-747 [Conf]
  19. Rui Tang, Fengming Zhang, Yong-Bin Kim
    QCA-based nano circuits design [adder design example]. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2005, pp:2527-2530 [Conf]
  20. Young-Jun Lee, Yong-Bin Kim
    A fast and precise interconnect capacitive coupling noise model. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2004, pp:873-876 [Conf]
  21. Dae Woon Kang, Yong-Bin Kim
    Design flow of robust routed power distribution for low power ASIC. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2002, pp:181-184 [Conf]
  22. Jihyun Lee, Yong-Bin Kim
    ASLIC: A Low Power CMOS Analog Circuit Design Automation. [Citation Graph (0, 0)][DBLP]
    ISQED, 2005, pp:470-475 [Conf]
  23. Young-Jun Lee, Jong-Jin Lim, Yong-Bin Kim
    A Novel Clocking Strategy for Dynamic Circuits. [Citation Graph (0, 0)][DBLP]
    ISQED, 2003, pp:307-312 [Conf]
  24. Minsu Choi, Hardy J. Pottinger, Nohpill Park, Yong-Bin Kim
    Need For Undergraduate And Graduate-Level Education In Testing Of Microelectronic Circuits And Systems. [Citation Graph (0, 0)][DBLP]
    MSE, 2003, pp:121-122 [Conf]
  25. Minsu Choi, Nohpill Park, Fabrizio Lombardi, Yong-Bin Kim, Vincenzo Piuri
    Optimal Spare Utilization in Repairable and Reliable Memory Cores. [Citation Graph (0, 0)][DBLP]
    MTDT, 2003, pp:64-71 [Conf]
  26. Minsu Choi, N.-J. Park, K. M. George, Byoungjae Jin, Nohpill Park, Yong-Bin Kim, Fabrizio Lombardi
    Fault Tolerant Memory Design for HW/SW Co-Reliability in Massively Parallel Computing Systems. [Citation Graph (0, 0)][DBLP]
    NCA, 2003, pp:341-0 [Conf]
  27. Minsu Choi, Nohpill Park, Yong-Bin Kim, Fabrizio Lombardi
    Hardware/Software Co-Reliability of Configurable Digital Systems. [Citation Graph (0, 0)][DBLP]
    PRDC, 2002, pp:67-74 [Conf]
  28. Soha Hassoun, Yong-Bin Kim, Fabrizio Lombardi
    Guest Editors' Introduction: Clockless VLSI Systems. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2003, v:20, n:6, pp:5-8 [Journal]
  29. Woo Jin Kim, Yong-Bin Kim
    Automating Wave-Pipelined Circuit Design. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2003, v:20, n:6, pp:51-58 [Journal]
  30. Jihyun Lee, Yong-Bin Kim
    ASLIC: A low power CMOS analog circuit design automation. [Citation Graph (0, 0)][DBLP]
    Integration, 2006, v:39, n:3, pp:157-181 [Journal]
  31. Minsu Choi, Nohpill Park, Vincenzo Piuri, Yong-Bin Kim, Fabrizio Lombardi
    Balanced dual-stage repair for dependable embedded memory cores. [Citation Graph (0, 0)][DBLP]
    Journal of Systems Architecture, 2004, v:50, n:5, pp:281-285 [Journal]
  32. Richard D. LeDuc, Gregory K. Taylor, Yong-Bin Kim, Thomas E. Januszyk, Lee H. Bynum, Joseph V. Sola, John S. Garavelli, Neil L. Kelleher
    ProSight PTM: an integrated environment for protein identification and characterization by top-down mass spectrometry. [Citation Graph (0, 0)][DBLP]
    Nucleic Acids Research, 2004, v:32, n:Web-Server-Issue, pp:340-345 [Journal]
  33. Woon Kang, Yong-Bin Kim, T. Doyle
    A high-efficiency fully digital synchronous buck converter power delivery system based on a finite-state machine. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2006, v:14, n:3, pp:229-240 [Journal]
  34. Rui Tang, Fengming Zhang, Yong-Bin Kim
    Design metal-dot based QCA circuits using SPICE model. [Citation Graph (0, 0)][DBLP]
    Microelectronics Journal, 2006, v:37, n:8, pp:821-827 [Journal]
  35. Fengming Zhang, Rui Tang, Yong-Bin Kim
    SET-based nano-circuit simulation and design method using HSPICE. [Citation Graph (0, 0)][DBLP]
    Microelectronics Journal, 2005, v:36, n:8, pp:741-748 [Journal]
  36. James T. Doyle, Young-Jun Lee, Yong-Bin Kim
    Fast and accurate DAC modeling techniques based on wavelet theory. [Citation Graph (0, 0)][DBLP]
    Microelectronics Journal, 2004, v:35, n:5, pp:451-460 [Journal]
  37. Yong-Bin Kim, Kyung Ki Kim, James T. Doyle
    A CMOS Low Power Fully Digital Adaptive Power Delivery System Based on Finite State Machine Control. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:1149-1152 [Conf]
  38. Kyung Ki Kim, Yong-Bin Kim
    Optimal Body Biasing for Minimum Leakage Power in Standby Mode. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:1161-1164 [Conf]
  39. Young-Jun Lee, Jihyun Lee, Kyung Ki Kim, Yong-Bin Kim, Joseph Ayers
    Low power CMOS electronic central pattern generator design for a biomimetic underwater robot. [Citation Graph (0, 0)][DBLP]
    Neurocomputing, 2007, v:71, n:1-3, pp:284-296 [Journal]

  40. Fault Tolerant Source Routing for Network-on-Chip. [Citation Graph (, )][DBLP]


  41. Defect-Tolerant Gate Macro Mapping & Placement in Clock-Free Nanowire Crossbar Architecture. [Citation Graph (, )][DBLP]


  42. Checkpointing of Rectilinear Growth in DNA Self-Assembly. [Citation Graph (, )][DBLP]


  43. Errors in DNA Self-Assembly by Synthesized Tile Sets. [Citation Graph (, )][DBLP]


  44. A Novel Hardened Design of a CMOS Memory Cell at 32nm. [Citation Graph (, )][DBLP]


  45. Low-power side-channel attack-resistant asynchronous S-box design for AES cryptosystems. [Citation Graph (, )][DBLP]


  46. A low leakage 9t sram cell for ultra-low power operation. [Citation Graph (, )][DBLP]


  47. Performance assessment of analog circuits with carbon nanotube FET (CNFET). [Citation Graph (, )][DBLP]


  48. A low-offset high-speed double-tail dual-rail dynamic latched comparator. [Citation Graph (, )][DBLP]


  49. Read-out schemes for a CNTFET-based crossbar memory. [Citation Graph (, )][DBLP]


  50. 8Gb/s capacitive low power and high speed 4-PWAM transceiver design. [Citation Graph (, )][DBLP]


  51. A novel all-digital fractional-N frequency synthesizer architecture with fast acquisition and low spur. [Citation Graph (, )][DBLP]


  52. Low power 8T SRAM using 32nm independent gate FinFET technology. [Citation Graph (, )][DBLP]


  53. A low power 32 nanometer CMOS digitally controlled oscillator. [Citation Graph (, )][DBLP]


  54. Leakage Minimization Technique for Nanoscale CMOS VLSI. [Citation Graph (, )][DBLP]


Search in 0.524secs, Finished in 0.529secs
NOTICE1
System may not be available sometimes or not working properly, since it is still in development with continuous upgrades
NOTICE2
The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP
 
System created by asidirop@csd.auth.gr [http://users.auth.gr/~asidirop/] © 2002
for Data Engineering Laboratory, Department of Informatics, Aristotle University © 2002