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Bill Lin: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Robert M. Fuhrer, Bill Lin, Steven M. Nowick
    Algorithms for the optimal state assignment of asynchronous state machines. [Citation Graph (0, 0)][DBLP]
    ARVLSI, 1995, pp:59-75 [Conf]
  2. Chantal Ykman-Couvreur, Bill Lin
    Optimised state assignment for asynchronous circuit synthesis. [Citation Graph (0, 0)][DBLP]
    ASYNC, 1995, pp:118-127 [Conf]
  3. Bill Lin, Steven Vercauteren, Hugo De Man
    Embedded Architecture Co-Synthesis and System Integration. [Citation Graph (0, 0)][DBLP]
    CODES, 1996, pp:2-9 [Conf]
  4. Gjalt G. de Jong, Bill Lin
    A Communicating Petri Net Model for the Design of Concurrent Asynchronous Modules. [Citation Graph (0, 0)][DBLP]
    DAC, 1994, pp:49-55 [Conf]
  5. Alex Kondratyev, Michael Kishinevsky, Bill Lin, Peter Vanbekbergen, Alexandre Yakovlev
    Basic Gate Implementation of Speed-Independent Circuits. [Citation Graph (0, 0)][DBLP]
    DAC, 1994, pp:56-62 [Conf]
  6. Bill Lin
    A System Design Methodology for Software/Hardware Co-Development of Telecommunication Network Applications. [Citation Graph (0, 0)][DBLP]
    DAC, 1996, pp:672-677 [Conf]
  7. Bill Lin
    Software Synthesis of Process-Based Concurrent Programs. [Citation Graph (0, 0)][DBLP]
    DAC, 1998, pp:502-505 [Conf]
  8. Bill Lin, Olivier Coudert, Jean Christophe Madre
    Symbolic Prime Generation for Multiple-Valued Functions. [Citation Graph (0, 0)][DBLP]
    DAC, 1992, pp:40-44 [Conf]
  9. Bill Lin, Gjalt G. de Jong, Tilman Kolks
    Hierarchical Optimization of Asynchronous Circuits. [Citation Graph (0, 0)][DBLP]
    DAC, 1995, pp:712-717 [Conf]
  10. B. Lin, A. Richard Newton
    KAHLUA: A Hierarchical Circuit Disassembler. [Citation Graph (0, 0)][DBLP]
    DAC, 1987, pp:311-317 [Conf]
  11. José C. Monteiro, Srinivas Devadas, Bill Lin
    A Methodology for Efficient Estimation of Switching Activity in Sequential Logic Circuits. [Citation Graph (0, 0)][DBLP]
    DAC, 1994, pp:12-17 [Conf]
  12. Milton H. Sawasaki, Chantal Ykman-Couvreur, Bill Lin
    Externally Hazard-Free Implementations of Asynchronous Circuits. [Citation Graph (0, 0)][DBLP]
    DAC, 1995, pp:718-724 [Conf]
  13. Steven Vercauteren, Bill Lin, Hugo De Man
    Constructing Application-Specific Heterogeneous Embedded Architectures from Custom HW/SW Applications. [Citation Graph (0, 0)][DBLP]
    DAC, 1996, pp:521-526 [Conf]
  14. Steven Vercauteren, Bill Lin, Hugo De Man
    A Strategy for Real-Time Kernel Support in Application-Specific HW/SW Embedded Architectures. [Citation Graph (0, 0)][DBLP]
    DAC, 1996, pp:678-683 [Conf]
  15. Eric Verlind, Gjalt G. de Jong, Bill Lin
    Efficient Partial Enumeration for Timing Analysis of Asynchronous Systems. [Citation Graph (0, 0)][DBLP]
    DAC, 1996, pp:55-58 [Conf]
  16. Eric Verlind, Tilman Kolks, Gjalt G. de Jong, Bill Lin, Hugo De Man
    A Time Abstraction Method for Efficient Verification of Communicating Systems. [Citation Graph (0, 0)][DBLP]
    DAC, 1994, pp:609-614 [Conf]
  17. Xiaohan Zhu, Bill Lin
    Hardware Compilation for FPGA-Based Configurable Computing Machines. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:697-702 [Conf]
  18. Bill Lin
    Efficient Compilation of Process-Based Concurrent Programs without Run-Time Scheduling. [Citation Graph (0, 0)][DBLP]
    DATE, 1998, pp:211-217 [Conf]
  19. Steven Vercauteren, Diederik Verkest, Gjalt G. de Jong, Bill Lin
    Efficient Verification using Generalized Partial Order Analysis. [Citation Graph (0, 0)][DBLP]
    DATE, 1998, pp:782-789 [Conf]
  20. Peter Vanbekbergen, Chantal Ykman-Couvreur, Bill Lin, Hugo De Man
    A Generalized Signal Transition Graph Model for Specification of Complex Interfaces. [Citation Graph (0, 0)][DBLP]
    EDAC-ETC-EUROASIC, 1994, pp:378-384 [Conf]
  21. Julio Leao da Silva Jr., Chantal Ykman-Couvreur, Bill Lin, Hugo De Man, Gjalt G. de Jong
    A System Design Methodology for Telecommunication Network Applications. [Citation Graph (0, 0)][DBLP]
    Great Lakes Symposium on VLSI, 1997, pp:64-69 [Conf]
  22. Bill Lin, Isaac Keslassy
    A Scalable Switch for Service Guarantees. [Citation Graph (0, 0)][DBLP]
    Hot Interconnects, 2005, pp:93-99 [Conf]
  23. Ranjita Bhagwan, Bill Lin
    Design of High-Speed Packet Switch with Fine-Grained Quality-of-Service Guarantees. [Citation Graph (0, 0)][DBLP]
    ICC (3), 2000, pp:1430-1434 [Conf]
  24. Robert M. Fuhrer, Bill Lin, Steven M. Nowick
    Symbolic hazard-free minimization and encoding of asynchronous finite state machines. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1995, pp:604-611 [Conf]
  25. Gert Goossens, Ivo Bolsens, Bill Lin, Francky Catthoor
    Design of heterogeneous ICs for mobile and personal communication systems. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1994, pp:524-531 [Conf]
  26. Gjalt G. de Jong, Bill Lin, Carl Verdonck, Sven Wuytack, Francky Catthoor
    Background memory management for dynamic data structure intensive processing systems. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1995, pp:515-520 [Conf]
  27. Tilman Kolks, Bill Lin, Hugo De Man
    Sizing and verification of communication buffers for communicating processes. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1993, pp:660-664 [Conf]
  28. Bill Lin, Srinivas Devadas
    Synthesis of hazard-free multi-level logic under multiple-input changes from binary decision diagrams. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1994, pp:542-549 [Conf]
  29. Bill Lin, Fabio Somenzi
    Minimization of Symbolic Relations. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1990, pp:88-91 [Conf]
  30. Bill Lin, Hervé J. Touati, A. Richard Newton
    Don't Care Minimization of Multi-Level Sequential Logic Networks. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1990, pp:414-417 [Conf]
  31. Bill Lin, Steven Vercauteren
    Synthesis of concurrent system interface modules with automatic protocol conversion generation. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1994, pp:101-108 [Conf]
  32. Peter Vanbekbergen, Bill Lin, Gert Goossens, Hugo De Man
    A generalized state assignment theory for transformation on signal transition graphs. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1992, pp:112-117 [Conf]
  33. Hervé J. Touati, Hamid Savoj, Bill Lin, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
    Implicit State Enumeration of Finite State Machines Using BDDs. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1990, pp:130-133 [Conf]
  34. Kenneth Y. Yun, Bill Lin, David L. Dill, Srinivas Devadas
    Performance-driven synthesis of asynchronous controllers. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1994, pp:550-557 [Conf]
  35. Bill Lin
    Efficient Symbolic Support Manipulation. [Citation Graph (0, 0)][DBLP]
    ICCD, 1993, pp:513-516 [Conf]
  36. Bill Lin, Hugo De Man
    Low-Power Driven Technology Mapping under Timing Constraints. [Citation Graph (0, 0)][DBLP]
    ICCD, 1993, pp:421-427 [Conf]
  37. Bill Lin, A. Richard Newton
    Implicit Manipulation of Equivalence Classes Using Binary Decision Diagrams. [Citation Graph (0, 0)][DBLP]
    ICCD, 1991, pp:81-85 [Conf]
  38. Chantal Ykman-Couvreur, Bill Lin
    Efficient state assignment framework for asynchronous state graphs. [Citation Graph (0, 0)][DBLP]
    ICCD, 1995, pp:692-0 [Conf]
  39. Xiaohan Zhu, Bill Lin
    Compositional Software Synthesis of Communicating Processes. [Citation Graph (0, 0)][DBLP]
    ICCD, 1999, pp:646-651 [Conf]
  40. Ranjita Bhagwan, Bill Lin
    Fast and Scalable Priority Queue Architecture for High-Speed Network Switches. [Citation Graph (0, 0)][DBLP]
    INFOCOM, 2000, pp:538-547 [Conf]
  41. Stefano Santi, Bill Lin, Ljupco Kocarev, Gian Mario Maggio, Riccardo Rovatti, Gianluca Setti
    On the impact of traffic statistics on quality of service for networks on chip. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2005, pp:2349-2352 [Conf]
  42. Steven Vercauteren, Diederik Verkest, Gjalt G. de Jong, Bill Lin
    Derivation of Formal Representations from Process-Based Specification and Implementation Models. [Citation Graph (0, 0)][DBLP]
    ISSS, 1997, pp:16-0 [Conf]
  43. Sven Wuytack, Francky Catthoor, Gjalt G. de Jong, Bill Lin, Hugo De Man
    Flow Graph Balancing for Minimizing the Required Memory Bandwidth. [Citation Graph (0, 0)][DBLP]
    ISSS, 1996, pp:127-132 [Conf]
  44. Bill Lin, A. Richard Newton
    Exact Redundant State Registers Removal Based on Binary Decision Diagrams. [Citation Graph (0, 0)][DBLP]
    VLSI, 1991, pp:277-286 [Conf]
  45. Bill Lin
    Compiling concurrent programs for embedded sequential execution. [Citation Graph (0, 0)][DBLP]
    Integration, 2007, v:40, n:2, pp:106-117 [Journal]
  46. Xuejun Du, Gary D. Hachtel, Bill Lin, A. Richard Newton
    MUSE: a multilevel symbolic encoding algorithm for state assignment. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1991, v:10, n:1, pp:28-38 [Journal]
  47. Bill Lin, Srinivas Devadas
    Synthesis of hazard-free multilevel logic under multiple-input changes from binary decision diagrams. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1995, v:14, n:8, pp:974-985 [Journal]
  48. Bill Lin, A. Richard Newton
    A circuit disassembly technique for synthesizing symbolic layouts from mask descriptions. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1990, v:9, n:9, pp:959-969 [Journal]
  49. Takayasu Sakurai, Bill Lin, A. Richard Newton
    Fast simulated diffusion: an optimization algorithm for multiminimum problems and its application to MOSFET model parameter extraction. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1992, v:11, n:2, pp:228-234 [Journal]
  50. Milton H. Sawasaki, Chantal Ykman-Couvreur, Bill Lin
    Externally hazard-free implementations of asynchronous control circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1997, v:16, n:8, pp:835-848 [Journal]
  51. Kenneth Y. Yun, Bill Lin, David L. Dill, Srinivas Devadas
    BDD-based synthesis of extended burst-mode controllers. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1998, v:17, n:9, pp:782-792 [Journal]
  52. Hao Wang, Bill Lin
    Pipelined van Emde Boas Tree: Algorithms, Analysis, and Applications. [Citation Graph (0, 0)][DBLP]
    INFOCOM, 2007, pp:2471-2475 [Conf]
  53. Bill Lin, Isaac Keslassy
    The Concurrent Matching Switch Architecture. [Citation Graph (0, 0)][DBLP]
    INFOCOM, 2006, pp:- [Conf]
  54. Shan Yan, Bill Lin
    Stream execution on wide-issue clustered VLIW architectures. [Citation Graph (0, 0)][DBLP]
    LCTES, 2007, pp:158-160 [Conf]
  55. Bill Lin, Wai-Shing Ho, Ben Kao, Chun Kit Chui
    Adaptive Frequency Counting over Bursty Data Streams. [Citation Graph (0, 0)][DBLP]
    CIDM, 2007, pp:516-523 [Conf]
  56. Hao Wang, Bill Lin
    On the Efficient Implementation of Pipelined Heaps for Network Processing. [Citation Graph (0, 0)][DBLP]
    GLOBECOM, 2006, pp:- [Conf]
  57. Chi-Ying Tsui, José C. Monteiro, Massoud Pedram, Srinivas Devadas, Alvin M. Despain, Bill Lin
    Power estimation methods for sequential logic circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1995, v:3, n:3, pp:404-416 [Journal]
  58. Chi-Ying Tsui, José C. Monteiro, Massoud Pedram, Srinivas Devadas, Alvin M. Despain, Bill Lin
    Correction to "Power Estimation Methods for Sequential Logic Circuits" [Correspondence]. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1996, v:4, n:4, pp:495- [Journal]

  59. Application-specific Network-on-Chip architecture synthesis based on set partitions and Steiner Trees. [Citation Graph (, )][DBLP]


  60. Trace-driven optimization of networks-on-chip configurations. [Citation Graph (, )][DBLP]


  61. A general state graph transformation framework for asynchronous synthesis. [Citation Graph (, )][DBLP]


  62. Near-optimal oblivious routing on three-dimensional mesh networks. [Citation Graph (, )][DBLP]


  63. Design of application-specific 3D Networks-on-Chip architectures. [Citation Graph (, )][DBLP]


  64. Design and Analysis of a Robust Pipelined Memory System. [Citation Graph (, )][DBLP]


  65. Network DVR: A Programmable Framework for Application-Aware Trace Collection. [Citation Graph (, )][DBLP]


  66. Proactive Surge Protection: A Defense Mechanism for Bandwidth-Based Attacks. [Citation Graph (, )][DBLP]


  67. Frame-aggregated concurrent matching switch. [Citation Graph (, )][DBLP]


  68. BRICK: a novel exact active statistics counter architecture. [Citation Graph (, )][DBLP]


  69. Design of a High-Throughput Distributed Shared-Buffer NoC Router. [Citation Graph (, )][DBLP]


  70. Birkhoff-von Neumann switching with statistical traffic profiles. [Citation Graph (, )][DBLP]


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