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Title:
Author:
Ganesh Gopalakrishnan: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Jae-Tack Yoo, Ganesh Gopalakrishnan, Kent F. Smith, V. John Mathews
    High speed counterflow-clocked pipelining illustrated on the design of HDTV subband vector quantizer chips. [Citation Graph (0, 0)][DBLP]
    ARVLSI, 1995, pp:91-107 [Conf]
  2. Hans M. Jacobson, Ganesh Gopalakrishnan
    Asynchronous Microengines for Efficient High-level Control. [Citation Graph (0, 0)][DBLP]
    ARVLSI, 1997, pp:201-218 [Conf]
  3. Hans M. Jacobson, Erik Brunvand, Ganesh Gopalakrishnan, Prabhakar Kudva
    High-Level Asynchronous System Design Using the ACK Framework. [Citation Graph (0, 0)][DBLP]
    ASYNC, 2000, pp:93-103 [Conf]
  4. Ganesh Gopalakrishnan, Narayana Mani, Venkatesh Akella
    Parallel Composition of Lockstep Synchronous Processes for Hardware Validation: Divide-and-Conquer Composition. [Citation Graph (0, 0)][DBLP]
    Automatic Verification Methods for Finite State Systems, 1989, pp:374-382 [Conf]
  5. Prosenjit Chatterjee, Hemanthkumar Sivaraj, Ganesh Gopalakrishnan
    Shared Memory Consistency Protocol Verification Against Weak Memory Models: Refinement via Model-Checking. [Citation Graph (0, 0)][DBLP]
    CAV, 2002, pp:123-136 [Conf]
  6. Ganesh Gopalakrishnan, Yue Yang, Hemanthkumar Sivaraj
    QB or Not QB: An Efficient Execution Verification Tool for Memory Orderings. [Citation Graph (0, 0)][DBLP]
    CAV, 2004, pp:401-413 [Conf]
  7. Ravi Hosabettu, Ganesh Gopalakrishnan, Mandayam K. Srivas
    Verifying Advanced Microarchitectures that Support Speculation and Exceptions. [Citation Graph (0, 0)][DBLP]
    CAV, 2000, pp:521-537 [Conf]
  8. Ravi Hosabettu, Mandayam K. Srivas, Ganesh Gopalakrishnan
    Decomposing the Proof of Correctness of pipelined Microprocessors. [Citation Graph (0, 0)][DBLP]
    CAV, 1998, pp:122-134 [Conf]
  9. Prabhat Jain, Prabhakar Kudva, Ganesh Gopalakrishnan
    Towards a Verification Technique for Large Synchronous Circuits. [Citation Graph (0, 0)][DBLP]
    CAV, 1992, pp:109-122 [Conf]
  10. Ratan Nalumasu, Rajnish Ghughal, Abdelillah Mokkedem, Ganesh Gopalakrishnan
    The 'Test Model-Checking' Approach to the Verification of Formal Memory Models of Multiprocessors. [Citation Graph (0, 0)][DBLP]
    CAV, 1998, pp:464-476 [Conf]
  11. Ganesh Gopalakrishnan, Rajnish Ghughal, Ravi Hosabettu, Abdelillah Mokkedem, Ratan Nalumasu
    Formal modeling and validation applied to a commercial coherent bus: a case study. [Citation Graph (0, 0)][DBLP]
    CHARME, 1997, pp:48-62 [Conf]
  12. Ravi Hosabettu, Ganesh Gopalakrishnan, Mandayam K. Srivas
    A Proof of Correctness of a Processor Implementing Tomasulo's Algorithm without a Reorder Buffer. [Citation Graph (0, 0)][DBLP]
    CHARME, 1999, pp:8-22 [Conf]
  13. Ritwik Bhattacharya, Steven M. German, Ganesh Gopalakrishnan
    Symbolic Partial Order Reduction for Rule Based Transition Systems. [Citation Graph (0, 0)][DBLP]
    CHARME, 2005, pp:332-335 [Conf]
  14. Sudhindra Pandav, Konrad Slind, Ganesh Gopalakrishnan
    Counterexample Guided Invariant Discovery for Parameterized Cache Coherence Verification. [Citation Graph (0, 0)][DBLP]
    CHARME, 2005, pp:317-331 [Conf]
  15. Yue Yang, Ganesh Gopalakrishnan, Gary Lindstrom, Konrad Slind
    Analyzing the Intel Itanium Memory Ordering Rules Using Logic Programming and SAT. [Citation Graph (0, 0)][DBLP]
    CHARME, 2003, pp:81-95 [Conf]
  16. Prabhakar Kudva, Ganesh Gopalakrishnan, Hans M. Jacobson
    A Technique for Synthesizing Distributed Burst-mode Circuits. [Citation Graph (0, 0)][DBLP]
    DAC, 1996, pp:67-70 [Conf]
  17. Prabhakar Kudva, Ganesh Gopalakrishnan, Hans M. Jacobson, Steven M. Nowick
    Synthesis for Hazard-free Customized CMOS Complex-Gate Networks Under Multiple-Input Changes. [Citation Graph (0, 0)][DBLP]
    DAC, 1996, pp:77-82 [Conf]
  18. Abdelillah Mokkedem, Ravi Hosabettu, Ganesh Gopalakrishnan
    Formalization and Proof of a Solution to the PCI 2.1 Bus Transaction Ordering Problem. [Citation Graph (0, 0)][DBLP]
    FMCAD, 1998, pp:237-254 [Conf]
  19. Prosenjit Chatterjee, Ganesh Gopalakrishnan
    A Specification and Verification Framework for Developing Weak Shared Memory Consistency Protocols. [Citation Graph (0, 0)][DBLP]
    FMCAD, 2002, pp:292-309 [Conf]
  20. Ratan Nalumasu, Ganesh Gopalakrishnan
    PV: An Explicit Enumeration Model-Checker. [Citation Graph (0, 0)][DBLP]
    FMCAD, 1998, pp:523-528 [Conf]
  21. Michael D. Jones, Ganesh Gopalakrishnan
    Verifying Transaction Ordering Properties in Unbounded Bus Networks through Combined Deductive/Algorithmic Methods. [Citation Graph (0, 0)][DBLP]
    FMCAD, 2000, pp:505-519 [Conf]
  22. Xiaofang Chen, Yu Yang, Ganesh Gopalakrishnan, Ching-Tsun Chou
    Reducing Verification Complexity of a Multicore Coherence Protocol Using Assume/Guarantee. [Citation Graph (0, 0)][DBLP]
    FMCAD, 2006, pp:81-88 [Conf]
  23. Robert Palmer, Ganesh Gopalakrishnan
    A Distributed Partial Order Reduction Algorithm. [Citation Graph (0, 0)][DBLP]
    FORTE, 2002, pp:370- [Conf]
  24. Venkatesh Akella, Ganesh Gopalakrishnan
    SHILPA: a high-level synthesis system for self-timed circuits. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1992, pp:587-591 [Conf]
  25. Hans M. Jacobson, Chris J. Myers, Ganesh Gopalakrishnan
    Achieving Fast and Exact Hazard-Free Logic Minimization of Extended Burst-Mode gC Finite State Machines. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2000, pp:303-310 [Conf]
  26. Prosenjit Chatterjee, Ganesh Gopalakrishnan
    towards A formal Model of Shared Memory Consistency for Intel ItaniumTM. [Citation Graph (0, 0)][DBLP]
    ICCD, 2001, pp:515-518 [Conf]
  27. Ganesh Gopalakrishnan, Prabhakar Kudva, Erik Brunvand
    Peephole Optimization of Asynchronous Macromodule Networks. [Citation Graph (0, 0)][DBLP]
    ICCD, 1994, pp:442-446 [Conf]
  28. Prabhat Jain, Ganesh Gopalakrishnan
    Some Techniques for Efficient Symbolic Simulation-Based Verification. [Citation Graph (0, 0)][DBLP]
    ICCD, 1992, pp:598-602 [Conf]
  29. Prabhat Jain, Ganesh Gopalakrishnan
    Hierarchical Constraint Solving in the Parametric Form with Applications to Efficient Symbolic Simulation Based Verification. [Citation Graph (0, 0)][DBLP]
    ICCD, 1993, pp:304-307 [Conf]
  30. Prabhakar Kudva, Ganesh Gopalakrishnan, Erik Brunvand, Venkatesh Akella
    Performance Analysis and Optimization of Asynchronous Circuits. [Citation Graph (0, 0)][DBLP]
    ICCD, 1994, pp:221-224 [Conf]
  31. Armin Liebchen, Ganesh Gopalakrishnan
    Dynamic Reordering of Hgh Latency Transactions Using a Modified a Micropipeline. [Citation Graph (0, 0)][DBLP]
    ICCD, 1992, pp:336-340 [Conf]
  32. Yue Yang, Ganesh Gopalakrishnan, Gary Lindstrom
    Memory-Model-Sensitive Data Race Analysis. [Citation Graph (0, 0)][DBLP]
    ICFEM, 2004, pp:30-45 [Conf]
  33. Rajnish Ghughal, Ganesh Gopalakrishnan
    Verification Methods for Weaker Shared Memory Consistency Models. [Citation Graph (0, 0)][DBLP]
    IPDPS Workshops, 2000, pp:985-992 [Conf]
  34. Ratan Nalumasu, Ganesh Gopalakrishnan
    Deriving Efficient Cache Coherence Protocols through Refinement. [Citation Graph (0, 0)][DBLP]
    IPPS/SPDP Workshops, 1998, pp:857-870 [Conf]
  35. Yue Yang, Ganesh Gopalakrishnan, Gary Lindstrom, Konrad Slind
    Nemos: A Framework for Axiomatic and Executable Specifications of Memory Consistency Models. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2004, pp:- [Conf]
  36. Ganesh Gopalakrishnan, Robert M. Kirby
    Toward reliable and efficient message passing software through formal analysis. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2006, pp:- [Conf]
  37. Richard Fujimoto, Jya-Jang Tsai, Ganesh Gopalakrishnan
    Design and Performance of Special Purpose Hardware for Time Warp. [Citation Graph (0, 0)][DBLP]
    ISCA, 1988, pp:401-408 [Conf]
  38. Yue Yang, Ganesh Gopalakrishnan, Gary Lindstrom
    Specifying Java thread semantics using a uniform memory model. [Citation Graph (0, 0)][DBLP]
    Java Grande, 2002, pp:192-201 [Conf]
  39. Ali Sezgin, Ganesh Gopalakrishnan
    On the decidability of shared memory consistency verification. [Citation Graph (0, 0)][DBLP]
    MEMOCODE, 2005, pp:199-208 [Conf]
  40. Ganesh Gopalakrishnan
    Synthesizing Synchronous Digital VLSI Controllers Using Petri Nets. [Citation Graph (0, 0)][DBLP]
    PNPM, 1987, pp:94-103 [Conf]
  41. Salman Pervez, Ganesh Gopalakrishnan, Robert M. Kirby, Rajeev Thakur, William D. Gropp
    Formal Verification of Programs That Use MPI One-Sided Communication. [Citation Graph (0, 0)][DBLP]
    PVM/MPI, 2006, pp:30-39 [Conf]
  42. Rajnish Ghughal, Abdelillah Mokkedem, Ratan Nalumasu, Ganesh Gopalakrishnan
    Using "Test Model-Checking" to Verify the Runway-PA8000 Memory Model. [Citation Graph (0, 0)][DBLP]
    SPAA, 1998, pp:231-239 [Conf]
  43. Ritwik Bhattacharya, Steven M. German, Ganesh Gopalakrishnan
    Exploiting Symmetry and Transactions for Partial Order Reduction of Rule Based Specifications. [Citation Graph (0, 0)][DBLP]
    SPIN, 2006, pp:252-270 [Conf]
  44. Igor Melatti, Robert Palmer, Geoffrey Sawaya, Yu Yang, Robert M. Kirby, Ganesh Gopalakrishnan
    Parallel and Distributed Model Checking in Eddy. [Citation Graph (0, 0)][DBLP]
    SPIN, 2006, pp:108-125 [Conf]
  45. Ganesh Gopalakrishnan, Venkatesh Akella
    A transformational approach to asynchronous high-level synthesis. [Citation Graph (0, 0)][DBLP]
    VLSI, 1993, pp:201-210 [Conf]
  46. Dominique Cansell, Ganesh Gopalakrishnan, Michael D. Jones, Dominique Méry, Airy Weinzoepflen
    Incremental Proof of the Producer/Consumer Property for the PCI Protocol. [Citation Graph (0, 0)][DBLP]
    ZB, 2002, pp:22-41 [Conf]
  47. Ganesh Gopalakrishnan, Sneha Kumar Kasera
    Robust rate based congestion control. [Citation Graph (0, 0)][DBLP]
    Computer Communication Review, 2002, v:32, n:3, pp:22- [Journal]
  48. Yue Yang, Ganesh Gopalakrishnan, Gary Lindstrom
    UMM: an operational memory model specification framework with integrated model checking capability. [Citation Graph (0, 0)][DBLP]
    Concurrency - Practice and Experience, 2005, v:17, n:5-6, pp:465-487 [Journal]
  49. Ganesh Gopalakrishnan
    Developing Micropipeline Wavefront Arbiters. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 1994, v:11, n:4, pp:55-64 [Journal]
  50. Ravi Hosabettu, Ganesh Gopalakrishnan, Mandayam K. Srivas
    A Practical Methodology for Verifying Pipelined Microarchitectures. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2003, v:20, n:4, pp:4-14 [Journal]
  51. Robert Palmer, Steve Barrus, Yu Yang, Ganesh Gopalakrishnan, Robert M. Kirby
    Gauss: A Framework for Verifying Scientific Computing Software. [Citation Graph (0, 0)][DBLP]
    Electr. Notes Theor. Comput. Sci., 2006, v:144, n:3, pp:95-106 [Journal]
  52. Hemanthkumar Sivaraj, Ganesh Gopalakrishnan
    Random Walk Based Heuristic Algorithms for Distributed Memory Model Checking. [Citation Graph (0, 0)][DBLP]
    Electr. Notes Theor. Comput. Sci., 2003, v:89, n:1, pp:- [Journal]
  53. Ganesh Gopalakrishnan, Warren A. Hunt Jr.
    Industrial Practice of Formal Hardware Verification: A Sampling. [Citation Graph (0, 0)][DBLP]
    Formal Methods in System Design, 2003, v:22, n:2, pp:95-99 [Journal]
  54. Ganesh Gopalakrishnan
    Introduction: Formal Methods for CAD: Enabling Technologies and System-level Applications. [Citation Graph (0, 0)][DBLP]
    Formal Methods in System Design, 2000, v:16, n:1, pp:5-6 [Journal]
  55. Ravi Hosabettu, Ganesh Gopalakrishnan, Mandayam K. Srivas
    Formal Verification of a Complex Pipelined Processor. [Citation Graph (0, 0)][DBLP]
    Formal Methods in System Design, 2003, v:23, n:2, pp:171-213 [Journal]
  56. Abdel Mokkedem, Ravi Hosabettu, Michael D. Jones, Ganesh Gopalakrishnan
    Formalization and Analysis of a Solution to the PCI 2.1 Bus Transaction Ordering Problem. [Citation Graph (0, 0)][DBLP]
    Formal Methods in System Design, 2000, v:16, n:1, pp:93-119 [Journal]
  57. Ratan Nalumasu, Ganesh Gopalakrishnan
    Deriving Efficient Cache Coherence Protocols Through Refinement. [Citation Graph (0, 0)][DBLP]
    Formal Methods in System Design, 2002, v:20, n:1, pp:107-125 [Journal]
  58. Ratan Nalumasu, Ganesh Gopalakrishnan
    An Efficient Partial Order Reduction Algorithm with an Alternative Proviso Implementation. [Citation Graph (0, 0)][DBLP]
    Formal Methods in System Design, 2002, v:20, n:3, pp:231-247 [Journal]
  59. Venkatesh Akella, Ganesh Gopalakrishnan
    CFSIM: A Concurrent Compiled Code Functional Simulator for hopCP. [Citation Graph (0, 0)][DBLP]
    Int. Journal in Computer Simulation, 1994, v:4, n:4, pp:0-0 [Journal]
  60. Ganesh Gopalakrishnan, Mandayam K. Srivas
    Implementing Functional Programs Using Mutable Abstract Data Types. [Citation Graph (0, 0)][DBLP]
    Inf. Process. Lett., 1988, v:26, n:6, pp:277-286 [Journal]
  61. Ali Sezgin, Ganesh Gopalakrishnan
    On the definition of sequential consistency. [Citation Graph (0, 0)][DBLP]
    Inf. Process. Lett., 2005, v:96, n:6, pp:193-196 [Journal]
  62. Annette Bunker, Ganesh Gopalakrishnan, Konrad Slind
    Live sequence charts applied to hardware requirements specification and verification. [Citation Graph (0, 0)][DBLP]
    STTT, 2005, v:7, n:4, pp:341-350 [Journal]
  63. Richard Fujimoto, Jya-Jang Tsai, Ganesh Gopalakrishnan
    Design and Evaluation of the Rollback Chip: Special Purpose Hardware for Time Warp. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1992, v:41, n:1, pp:68-82 [Journal]
  64. Ganesh Gopalakrishnan, Erik Brunvand, Nick Michell, Steven M. Nowick
    A correctness criterion for asynchronous circuit validation and optimization. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1994, v:13, n:11, pp:1309-1318 [Journal]
  65. Prabhat Jain, Ganesh Gopalakrishnan
    Efficient symbolic simulation-based verification using the parametric form of Boolean expressions. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1994, v:13, n:8, pp:1005-1015 [Journal]
  66. Ganesh Gopalakrishnan, Richard Fujimoto
    Design and Verification of the Rollback Chip Using HOP: A Case Study of Formal Methods Applied to Hardware design. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Comput. Syst., 1993, v:11, n:2, pp:109-145 [Journal]
  67. Annette Bunker, Ganesh Gopalakrishnan, Sally A. McKee
    Formal hardware specification languages for protocol compliance verification. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2004, v:9, n:1, pp:1-32 [Journal]
  68. Venkatesh Akella, Ganesh Gopalakrishnan
    Specification and Validation of Control-Intensive IC's in hopCP. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Software Eng., 1994, v:20, n:6, pp:405-423 [Journal]
  69. Ganesh Gopalakrishnan, Robert M. Kirby
    Formal Analysis for Debugging and Performance Optimization of MPI. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2007, pp:1-6 [Conf]
  70. Salman Pervez, Ganesh Gopalakrishnan, Robert M. Kirby, Robert Palmer, Rajeev Thakur, William Gropp
    Practical Model-Checking Method for Verifying Correctness of MPI Programs. [Citation Graph (0, 0)][DBLP]
    PVM/MPI, 2007, pp:344-353 [Conf]
  71. Yu Yang, Xiaofang Chen, Ganesh Gopalakrishnan, Robert M. Kirby
    Distributed Dynamic Partial Order Reduction Based Verification of Threaded Software. [Citation Graph (0, 0)][DBLP]
    SPIN, 2007, pp:58-75 [Conf]
  72. Ganesh Gopalakrishnan, John O'Leary
    Preface. [Citation Graph (0, 0)][DBLP]
    Electr. Notes Theor. Comput. Sci., 2007, v:174, n:9, pp:1-4 [Journal]
  73. Ganesh Gopalakrishnan, Prabhakar Kudva, Erik Brunvand
    Peephole optimization of asynchronous macromodule networks. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1999, v:7, n:1, pp:30-37 [Journal]
  74. Jae-Tack Yoo, Ganesh Gopalakrishnan, Kent F. Smith
    Timing constraints for high-speed counterflow-clocked pipelining. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1999, v:7, n:2, pp:167-173 [Journal]

  75. Dynamic Model Checking with Property Driven Pruning to Detect Race Conditions. [Citation Graph (, )][DBLP]


  76. Dynamic Verification of MPI Programs with Reductions in Presence of Split Operations and Relaxed Orderings. [Citation Graph (, )][DBLP]


  77. Reduced Execution Semantics of MPI: From Theory to Practice. [Citation Graph (, )][DBLP]


  78. Transaction Based Modeling and Verification of Hardware Protocols. [Citation Graph (, )][DBLP]


  79. MCC: A runtime verification tool for MCAPI user applications. [Citation Graph (, )][DBLP]


  80. Runtime verification methods for MPI. [Citation Graph (, )][DBLP]


  81. Some resources for teaching concurrency. [Citation Graph (, )][DBLP]


  82. Semantics driven dynamic partial-order reduction of MPI-based parallel programs. [Citation Graph (, )][DBLP]


  83. Scheduling considerations for building dynamic verification tools for MPI. [Citation Graph (, )][DBLP]


  84. Formal specification of the MPI-2.0 standard in TLA+. [Citation Graph (, )][DBLP]


  85. ISP: a tool for model checking MPI programs. [Citation Graph (, )][DBLP]


  86. A symbolic verifier for CUDA programs. [Citation Graph (, )][DBLP]


  87. Formal verification of practical MPI programs. [Citation Graph (, )][DBLP]


  88. A Formal Approach to Detect Functionally Irrelevant Barriers in MPI Programs. [Citation Graph (, )][DBLP]


  89. Implementing Efficient Dynamic Formal Verification Methods for MPI Programs. [Citation Graph (, )][DBLP]


  90. Sound and Efficient Dynamic Verification of MPI Programs with Probe Non-determinism. [Citation Graph (, )][DBLP]


  91. Practical Formal Verification of MPI and Thread Programs. [Citation Graph (, )][DBLP]


  92. How Formal Dynamic Verification Tools Facilitate Novel Concurrency Visualizations. [Citation Graph (, )][DBLP]


  93. Static-Analysis Assisted Dynamic Verification of MPI Waitany Programs (Poster Abstract). [Citation Graph (, )][DBLP]


  94. Efficient Stateful Dynamic Partial Order Reduction. [Citation Graph (, )][DBLP]


  95. Automatic Discovery of Transition Symmetry in Multithreaded Programs Using Dynamic Analysis. [Citation Graph (, )][DBLP]


  96. An Approach to Formalization and Analysis of Message Passing Libraries. [Citation Graph (, )][DBLP]


  97. Formal Methods for MPI Programs. [Citation Graph (, )][DBLP]


  98. Preface. [Citation Graph (, )][DBLP]


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