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Ranga Vemuri: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Sree Ganesan, Ranga Vemuri
    Analog-Digital Partitioning for Field-Programmable Mixed Signal Systems. [Citation Graph (0, 0)][DBLP]
    ARVLSI, 2001, pp:172-187 [Conf]
  2. Naren Narasimhan, Vinoo Srinivasan, Madhavi Vootukuru, Jeffrey Walrath, Sriram Govindarajan, Ranga Vemuri
    Rapid Prototyping of Reconfigurable Coprocessors. [Citation Graph (0, 0)][DBLP]
    ASAP, 1996, pp:303-312 [Conf]
  3. Srinivasan Dasasathyan, Rajesh Radhakrishnan, Ranga Vemuri
    Framework for Synthesis of Virtual Pipelines. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2002, pp:326-331 [Conf]
  4. Nagu R. Dhanwada, Adrián Núñez-Aldana, Ranga Vemuri
    Automatic Constraint Transformation with Integrated Parameter Space Exploration in Analog System Synthesis. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 1999, pp:153-156 [Conf]
  5. Mengmeng Ding, Glenn Wolfe, Ranga Vemuri
    An error-driven adaptive grid refinement algorithm for automatic generation of analog circuit performance macromodels. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2005, pp:477-482 [Conf]
  6. Xin Jia, Ranga Vemuri
    Using GALS architecture to reduce the impact of long wire delay on FPGA performance. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2005, pp:1260-1263 [Conf]
  7. Huiying Yang, Mukesh Ranjan, Wim Verhaegen, Mengmeng Ding, Ranga Vemuri, Georges G. E. Gielen
    Efficient symbolic sensitivity analysis of analog circuits using element-coefficient diagrams. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2005, pp:230-235 [Conf]
  8. Ranga Vemuri, Anuradha Sridhar
    Temporal Precondition Verification of Design Transformations. [Citation Graph (0, 0)][DBLP]
    CAV, 1991, pp:125-135 [Conf]
  9. Rajesh Radhakrishnan, Elena Teica, Ranga Vemuri
    Verification of Basic Block Schedules Using RTL Transformations. [Citation Graph (0, 0)][DBLP]
    CHARME, 2001, pp:173-178 [Conf]
  10. Ram Mandayam, Ranga Vemuri
    Performance Specification and Measurement. [Citation Graph (0, 0)][DBLP]
    CHDL, 1993, pp:281-298 [Conf]
  11. Karam S. Chatha, Ranga Vemuri
    MAGELLAN: multiway hardware-software partitioning and scheduling for latency minimization of hierarchical control-dataflow task graphs. [Citation Graph (0, 0)][DBLP]
    CODES, 2001, pp:42-47 [Conf]
  12. Karam S. Chatha, Ranga Vemuri
    RECOD: a retiming heuristic to optimize resource and memory utilization in HW/SW codesigns. [Citation Graph (0, 0)][DBLP]
    CODES, 1998, pp:139-143 [Conf]
  13. Xin Jia, Ranga Vemuri
    A Design Methodology for Self-Timed Event Logic Pipelines. [Citation Graph (0, 0)][DBLP]
    ESA/VLSI, 2004, pp:475-479 [Conf]
  14. Anuradha Agarwal, Hemanth Sampath, Veena Yelamanchili, Ranga Vemuri
    Fast and accurate parasitic capacitance models for layout-aware. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:145-150 [Conf]
  15. Mengmeng Ding, Ranga Vemuri
    A combined feasibility and performance macromodel for analog circuits. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:63-68 [Conf]
  16. Alex Doboli, Adrián Núñez-Aldana, Nagu R. Dhanwada, Sree Ganesan, Ranga Vemuri
    Behavioral Synthesis of Analog Systems Using Two-layered Design Space Exploration. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:951-957 [Conf]
  17. Alex Doboli, Ranga Vemuri
    Integrated High-Level Synthesis and Power-Net Routing for Digital Design under Switching Noise Constraints. [Citation Graph (0, 0)][DBLP]
    DAC, 2001, pp:629-634 [Conf]
  18. Rajiv Dutta, Jayanta Roy, Ranga Vemuri
    Distributed Design-Space Exploration for High-Level Synthesis Systems. [Citation Graph (0, 0)][DBLP]
    DAC, 1992, pp:644-650 [Conf]
  19. Sree Ganesan, Ranga Vemuri
    Behavioral Partitioning in the Synthesis of Mixed Analog-Digital Systems. [Citation Graph (0, 0)][DBLP]
    DAC, 2001, pp:133-138 [Conf]
  20. Manish Handa, Ranga Vemuri
    An efficient algorithm for finding empty space for online FPGA placement. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:960-965 [Conf]
  21. Meenakshi Kaul, Ranga Vemuri, Sriram Govindarajan, Iyad Ouaiss
    An Automated Temporal Partitioning and Loop Fission Approach for FPGA Based Reconfigurable Synthesis of DSP Applications. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:616-622 [Conf]
  22. Ram Mandayam, Ranga Vemuri
    Performance Specification Using Attributed Grammars. [Citation Graph (0, 0)][DBLP]
    DAC, 1993, pp:661-667 [Conf]
  23. Ranga Vemuri, Paddy Mamtora, Praveen Sinha, Nand Kumar, Jayanta Roy, Raghu Vutukuru
    Experiences in Functional Validation of a High Level Synthesis System. [Citation Graph (0, 0)][DBLP]
    DAC, 1993, pp:194-201 [Conf]
  24. Jeffrey Walrath, Ranga Vemuri
    Symbolic Evaluation of Performance Models for Tradeoff Visualization. [Citation Graph (0, 0)][DBLP]
    DAC, 1997, pp:359-364 [Conf]
  25. Raoul F. Badaoui, Ranga Vemuri
    Multi-Placement Structures for Fast and Optimized Placement in Analog Circuit Synthesis. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:138-143 [Conf]
  26. Anuradha Agarwal, Hemanth Sampath, Veena Yelamanchili, Ranga Vemuri
    Accurate Estimation of Parasitic Capacitances in Analog Circuits. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:1364-1365 [Conf]
  27. Amitava Bhaduri, Ranga Vemuri
    Inductive and Capacitive Coupling Aware Routing Methodology Driven by a Higher Order RLCK Moment Metric. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:922-923 [Conf]
  28. Nagu R. Dhanwada, Adrián Núñez-Aldana, Ranga Vemuri
    Hierarchical Constraint Transformation Using Directed Interval Search for Analog System Synthesis. [Citation Graph (0, 0)][DBLP]
    DATE, 1999, pp:328-0 [Conf]
  29. Mengmeng Ding, Ranga Vemuri
    A Two-Level Modeling Approach to Analog Circuit Performance Macromodeling. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:1088-1089 [Conf]
  30. Alex Doboli, Ranga Vemuri
    A regularity-based hierarchical symbolic analysis method for large-scale analog networks. [Citation Graph (0, 0)][DBLP]
    DATE, 2001, pp:806- [Conf]
  31. Alex Doboli, Ranga Vemuri
    A Functional Specification Notation for Co-Design of Mixed Analog-Digital Systems. [Citation Graph (0, 0)][DBLP]
    DATE, 2002, pp:760-769 [Conf]
  32. Alex Doboli, Ranga Vemuri
    A VHDL-AMS Compiler and Architecture Generator for Behavioral Synthesis of Analog Systems. [Citation Graph (0, 0)][DBLP]
    DATE, 1999, pp:338-345 [Conf]
  33. Sree Ganesan, Ranga Vemuri
    Technology Mapping and Retargeting for Field-Programmable Analog Arrays. [Citation Graph (0, 0)][DBLP]
    DATE, 2000, pp:58-0 [Conf]
  34. Satish Ganesan, Ranga Vemuri
    An Integrated Temporal Partitioning and Partial Reconfiguration Technique for Design Latency Improvement. [Citation Graph (0, 0)][DBLP]
    DATE, 2000, pp:320-325 [Conf]
  35. Sriram Govindarajan, Ranga Vemuri
    Improving the Schedule Quality of Static-List Time-Constrained Scheduling. [Citation Graph (0, 0)][DBLP]
    DATE, 2000, pp:749- [Conf]
  36. Manish Handa, Ranga Vemuri
    A Fast Algorithm for Finding Maximal Empty Rectangles for Dynamic FPGA Placement. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:744-745 [Conf]
  37. Meenakshi Kaul, Ranga Vemuri
    Optimal Temporal Partitioning and Synthesis for Reconfigurable Architectures. [Citation Graph (0, 0)][DBLP]
    DATE, 1998, pp:389-0 [Conf]
  38. Meenakshi Kaul, Ranga Vemuri
    Temporal Partitioning combined with Design Space Exploration for Latency Minimization of Run-Time Reconfigured Designs. [Citation Graph (0, 0)][DBLP]
    DATE, 1999, pp:202-209 [Conf]
  39. Jawad Khan, Ranga Vemuri
    An Iterative Algorithm for Battery-Aware Task Scheduling on Portable Computing Platforms. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:622-627 [Conf]
  40. Nazanin Mansouri, Ranga Vemuri
    Accounting for Various Register Allocation Schemes During Post-Synthesis Verification of RTL Designs. [Citation Graph (0, 0)][DBLP]
    DATE, 1999, pp:223-0 [Conf]
  41. Adrián Núñez-Aldana, Ranga Vemuri
    An Analog Performance Estimator for Improving the Effectiveness of CMOS Analog Systems Circuit Synthesis. [Citation Graph (0, 0)][DBLP]
    DATE, 1999, pp:406-411 [Conf]
  42. Iyad Ouaiss, Ranga Vemuri
    Efficient Resource Arbitration in Reconfigurable Computing Environments. [Citation Graph (0, 0)][DBLP]
    DATE, 2000, pp:560-566 [Conf]
  43. Iyad Ouaiss, Ranga Vemuri
    Hierarchical memory mapping during synthesis in FPGA-based reconfigurable computers. [Citation Graph (0, 0)][DBLP]
    DATE, 2001, pp:650-657 [Conf]
  44. Mukesh Ranjan, Wim Verhaegen, Anuradha Agarwal, Hemanth Sampath, Ranga Vemuri, Georges G. E. Gielen
    Fast, Layout-Inclusive Analog Circuit Synthesis using Pre-Compiled Parasitic-Aware Symbolic Performance Models. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:604-609 [Conf]
  45. Balasubramanian Sethuraman, Ranga Vemuri
    optiMap: a tool for automated generation of noc architectures using multi-port routers for FPGAs. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:947-952 [Conf]
  46. Vinoo Srinivasan, Shankar Radhakrishnan, Ranga Vemuri
    Hardware Software Partitioning with Integrated Hardware Design Space Exploration. [Citation Graph (0, 0)][DBLP]
    DATE, 1998, pp:28-35 [Conf]
  47. Elena Teica, Rajesh Radhakrishnan, Ranga Vemuri
    On the verification of synthesized designs using automatically generated transformational witnesses. [Citation Graph (0, 0)][DBLP]
    DATE, 2001, pp:798- [Conf]
  48. Huiying Yang, Ranga Vemuri
    Efficient temperature-dependent symbolic sensitivity analysis and symbolic performance evaluation in analog circuit synthesis. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:283-284 [Conf]
  49. Manish Handa, Ranga Vemuri
    Area Fragmentation in Reconfigurable Operating Systems. [Citation Graph (0, 0)][DBLP]
    ERSA, 2004, pp:77-83 [Conf]
  50. Jawad Khan, Jayanthi Rajagopalan, Renqiu Huang, Ranga Vemuri
    A Portable Face Recognition System Using Reconfigurable Hardware. [Citation Graph (0, 0)][DBLP]
    ERSA, 2004, pp:213-217 [Conf]
  51. Jawad Khan, Balasubramanian Sethuraman, Ranga Vemuri
    A Power-Performance Trade-off Methodology for Portable Reconfigurable Platforms. [Citation Graph (0, 0)][DBLP]
    ERSA, 2004, pp:33-37 [Conf]
  52. Sriram Govindarajan, Iyad Ouaiss, Meenakshi Kaul, Vinoo Srinivasan, Ranga Vemuri
    An Effective Design System for Dynamically Reconfigurable Architectures. [Citation Graph (0, 0)][DBLP]
    FCCM, 1998, pp:312-313 [Conf]
  53. Xin Jia, Ranga Vemuri
    The GAPLA: A Globally Asynchronous Locally Synchronous FPGA Architecture. [Citation Graph (0, 0)][DBLP]
    FCCM, 2005, pp:291-292 [Conf]
  54. Vinoo Srinivasan, Ranga Vemuri
    Task-Level Partitioning and RTL Design Space Exploration for Multi-FPGA Architectures. [Citation Graph (0, 0)][DBLP]
    FCCM, 1999, pp:272-0 [Conf]
  55. Nazanin Mansouri, Ranga Vemuri
    A Methodology for Automated Verification of Synthesized RTL Designs and Its Integration with a High-Level Synthesis Tool. [Citation Graph (0, 0)][DBLP]
    FMCAD, 1998, pp:204-221 [Conf]
  56. Naren Narasimhan, Ranga Vemuri
    Specification of Control Flow Properties for Verification of Synthesized VHDL Designs. [Citation Graph (0, 0)][DBLP]
    FMCAD, 1996, pp:327-345 [Conf]
  57. Vinoo Srinivasan, Ranga Vemuri
    Throughput Optimization with Design Space Exploration During Partitioning for Multi-FPGA Architectures. [Citation Graph (0, 0)][DBLP]
    FPGA, 1999, pp:253- [Conf]
  58. Karam S. Chatha, Ranga Vemuri
    Hardware-Software Codesign for Dynamically Reconfigurable Architectures. [Citation Graph (0, 0)][DBLP]
    FPL, 1999, pp:175-184 [Conf]
  59. Manish Handa, Ranga Vemuri
    An Integrated Online Scheduling and Placement Methodology. [Citation Graph (0, 0)][DBLP]
    FPL, 2004, pp:444-453 [Conf]
  60. Sriram Govindarajan, Ranga Vemuri
    Tightly Integrated Design Space Exploration with Spatial and Temporal Partitioning in SPARCS. [Citation Graph (0, 0)][DBLP]
    FPL, 2000, pp:7-18 [Conf]
  61. Renqiu Huang, Manish Handa, Ranga Vemuri
    Analysis of a Hybrid Interconnect Architecture for Dynamically Reconfigurable FPGAs. [Citation Graph (0, 0)][DBLP]
    FPL, 2004, pp:900-905 [Conf]
  62. Renqiu Huang, Ranga Vemuri
    PAHLS: Towards Run-Time Synthesis for FPGAs. [Citation Graph (0, 0)][DBLP]
    FPL, 2005, pp:739-740 [Conf]
  63. Xin Jia, Jayanthi Rajagopalan, Ranga Vemuri
    A Dynamically Reconfigurable Asynchronous FPGA Architecture. [Citation Graph (0, 0)][DBLP]
    FPL, 2004, pp:836-841 [Conf]
  64. Xin Jia, Ranga Vemuri
    A Novel Asynchronous FPGA Architecture Design and Its Performance Evaluation. [Citation Graph (0, 0)][DBLP]
    FPL, 2005, pp:287-292 [Conf]
  65. Amit Kasat, Iyad Ouaiss, Ranga Vemuri
    Memory Synthesis for FPGA-Based Reconfigurable Computers. [Citation Graph (0, 0)][DBLP]
    FPL, 2001, pp:70-80 [Conf]
  66. Jawad Khan, Manish Handa, Ranga Vemuri
    iPACE-V1: A Portable Adaptive Computing Engine for Real Time Applications. [Citation Graph (0, 0)][DBLP]
    FPL, 2002, pp:69-78 [Conf]
  67. Jawad Khan, Ranga Vemuri
    An Efficient Battery-Aware Task Scheduling Methodology for Portable RC Platforms. [Citation Graph (0, 0)][DBLP]
    FPL, 2004, pp:669-678 [Conf]
  68. Jawad Khan, Ranga Vemuri
    Energy Management in Battery-Powered Sensor Networks with Reconfigurable Computing Nodes. [Citation Graph (0, 0)][DBLP]
    FPL, 2005, pp:543-546 [Conf]
  69. Amitava Bhaduri, Ranga Vemuri
    Moment-driven coupling-aware routing methodology. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2005, pp:390-395 [Conf]
  70. Anuradha Agarwal, Glenn Wolfe, Ranga Vemuri
    Accuracy driven performance macromodeling of feasible regions during synthesis of analog circuits. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2005, pp:482-487 [Conf]
  71. Raoul F. Badaoui, Hemanth Sampath, Anuradha Agarwal, Ranga Vemuri
    A high level language for pre-layout extraction in parasite-aware analog circuit synthesis. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2004, pp:271-276 [Conf]
  72. Abhijit Ghosh, Sandeep K. Lodha, Ranga Vemuri
    Hierarchical Scheduling in High Level Synthesis Using Resource Sharing Across Nested Loops. [Citation Graph (0, 0)][DBLP]
    Great Lakes Symposium on VLSI, 1999, pp:140-143 [Conf]
  73. Renqiu Huang, Ranga Vemuri
    Transformation synthesis for data intensive applications to FPGAs. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2006, pp:349-352 [Conf]
  74. Srinivas Katkoori, Ranga Vemuri
    Accurate Resource Estimation Algorithms for Behavioral Synthesis. [Citation Graph (0, 0)][DBLP]
    Great Lakes Symposium on VLSI, 1999, pp:338-339 [Conf]
  75. Balasubramanian Sethuraman, Prasun Bhattacharya, Jawad Khan, Ranga Vemuri
    LiPaR: A light-weight parallel router for FPGA-based networks-on-chip. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2005, pp:452-457 [Conf]
  76. Anuradha Agarwal, Ranga Vemuri
    Hierarchical performance macromodels of feasible regions for synthesis of analog and RF circuits. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2005, pp:430-436 [Conf]
  77. Renqiu Huang, Ranga Vemuri
    Analysis and evaluation of a hybrid interconnect structure for FPGAs. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2004, pp:595-601 [Conf]
  78. Ranga Vemuri, Glenn Wolfe
    Adaptive sampling and modeling of analog circuit performance parameters with pseudo-cubic splines. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2004, pp:931-938 [Conf]
  79. Xin Jia, Ranga Vemuri
    Studying a GALS FPGA architecture using a parameterized automatic design flow. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2006, pp:688-693 [Conf]
  80. Anuradha Agarwal, Ranga Vemuri
    Layout-Aware RF Circuit Synthesis Driven by Worst Case Parasitic Corners. [Citation Graph (0, 0)][DBLP]
    ICCD, 2005, pp:444-452 [Conf]
  81. Sree Ganesan, Ranga Vemuri
    A Methodology for Rapid Prototyping of Analog Systems. [Citation Graph (0, 0)][DBLP]
    ICCD, 1999, pp:482-488 [Conf]
  82. Abhijit Ghosh, Ranga Vemuri
    Formal Verification of Synthesized Analog Designs. [Citation Graph (0, 0)][DBLP]
    ICCD, 1999, pp:40-45 [Conf]
  83. Sriram Govindarajan, Ranga Vemuri
    Dynamic Bounding of Successor Force Computations in the Force Directed List Scheduling Algorithms. [Citation Graph (0, 0)][DBLP]
    ICCD, 1997, pp:752-757 [Conf]
  84. Srinivas Katkoori, Nand Kumar, Ranga Vemuri
    High level profiling based low power synthesis technique. [Citation Graph (0, 0)][DBLP]
    ICCD, 1995, pp:446-0 [Conf]
  85. Madhubanti Mukherjee, Ranga Vemuri
    A Novel Synthesis Strategy Driven by Partial Evaluation Based Circuit Reduction for Application Specific DSP Circuits. [Citation Graph (0, 0)][DBLP]
    ICCD, 2003, pp:436-440 [Conf]
  86. Madhubanti Mukherjee, Ranga Vemuri
    Simultaneous Scheduling, Binding and Layer Assignment for Synthesis of Vertically Integrated 3D Systems. [Citation Graph (0, 0)][DBLP]
    ICCD, 2004, pp:222-227 [Conf]
  87. Adrián Núñez-Aldana, Ranga Vemuri
    A Linear Programming Approach for Synthesis of Mixed-Signal Interface Elements. [Citation Graph (0, 0)][DBLP]
    VLSI, 1999, pp:318-32 [Conf]
  88. Alex Doboli, Ranga Vemuri
    A Decomposition-based Symbolic Analysis Method for Analog Synthesis from Behavioral Specifications. [Citation Graph (0, 0)][DBLP]
    VLSI, 1999, pp:305-317 [Conf]
  89. Manish Handa, Ranga Vemuri
    Hardware Assisted Two Dimensional Ultra Fast Placement. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2004, pp:- [Conf]
  90. Renqiu Huang, Ranga Vemuri
    Forward-Looking Macro Generation and Relational Placement During High Level Synthesis to FPGAs. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2004, pp:- [Conf]
  91. Meenakshi Kaul, Ranga Vemuri
    Integrated Block-Processing and Design-Space Exploration in Temporal Partitioning for RTR Architectures. [Citation Graph (0, 0)][DBLP]
    IPPS/SPDP Workshops, 1999, pp:606-615 [Conf]
  92. Jawad Khan, Ranga Vemuri
    Battery-Efficient Task Execution on Reconfigurable Computing Platforms with Multiple Processing Units. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2005, pp:- [Conf]
  93. Preetham Lakshmikanthan, Sriram Govindarajan, Vinoo Srinivasan, Ranga Vemuri
    Behavioral Partitioning with Synthesis for Multi-FPGA Architectures under Interconnect, Area, and Latency Constraints. [Citation Graph (0, 0)][DBLP]
    IPDPS Workshops, 2000, pp:924-931 [Conf]
  94. Iyad Ouaiss, Sriram Govindarajan, Vinoo Srinivasan, Meenakshi Kaul, Ranga Vemuri
    An Integrated Partitioning and Synthesis System for Dynamically Reconfigurable Multi-FPGA Architectures. [Citation Graph (0, 0)][DBLP]
    IPPS/SPDP Workshops, 1998, pp:31-36 [Conf]
  95. Iyad Ouaiss, Ranga Vemuri
    Global memory mapping for FPGA-based reconfigurable systems. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2001, pp:144- [Conf]
  96. Yi Pan, Jie Li, Ranga Vemuri
    Continous Wavelet Transform on Reconfigurable Meshes. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2001, pp:114- [Conf]
  97. Vinoo Srinivasan, Shankar Radhakrishnan, Ranga Vemuri, Jeffrey Walrath
    Interconnect Synthesis for Reconfigurable Multi-FPGA Architectures. [Citation Graph (0, 0)][DBLP]
    IPPS/SPDP Workshops, 1999, pp:588-596 [Conf]
  98. Jeffrey Walrath, Ranga Vemuri
    A Performance Modeling and Analysis Environment for Reconfigurable Computers. [Citation Graph (0, 0)][DBLP]
    IPPS/SPDP Workshops, 1998, pp:19-24 [Conf]
  99. Raoul F. Badaoui, Ranga Vemuri
    Analog VLSI circuit-level synthesis using multi-placement structures. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 2005, pp:5978-5981 [Conf]
  100. S. Saha, Ranga Vemuri
    Use of adaptive integer-to-integer wavelet transforms in lossless image coding. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2001, pp:393-396 [Conf]
  101. Alex Doboli, Ranga Vemuri
    Hierarchical performance optimization for synthesis of linear analog systems. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2001, pp:431-434 [Conf]
  102. Nagu R. Dhanwada, Adrián Núñez-Aldana, Ranga Vemuri
    A genetic approach to simultaneous parameter space exploration and constraint transformation in analog synthesis. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 1999, pp:362-365 [Conf]
  103. Srinivas Katkoori, Ranga Vemuri
    Simulation based architectural power estimation for PLA-based controllers. [Citation Graph (0, 0)][DBLP]
    ISLPED, 1996, pp:121-124 [Conf]
  104. Shubhankar Basu, Priyanka Thakore, Ranga Vemuri
    Process Variation Tolerant Standard Cell Library Development Using Reduced Dimension Statistical Modeling and Optimization Techniques. [Citation Graph (0, 0)][DBLP]
    ISQED, 2007, pp:814-820 [Conf]
  105. Karam S. Chatha, Ranga Vemuri
    A Tool for Partitioning and Pipelined Scheduling of Hardware-Software Systems. [Citation Graph (0, 0)][DBLP]
    ISSS, 1998, pp:145-151 [Conf]
  106. Renqiu Huang, Ranga Vemuri
    Sensitivity Analysis of a Cluster-Based Interconnect Model for FPGAs. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2005, pp:250-251 [Conf]
  107. Huiying Yang, Anuradha Agarwal, Ranga Vemuri
    Fast Analog Circuit Synthesis Using Multiparameter Sensitivity Analysis Based on Element-Coefficient Diagrams. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2005, pp:71-76 [Conf]
  108. Vijay Sundaresan, Ranga Vemuri
    A Novel Approach to Performance-Oriented Datapath Allocation and Floorplanning. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2006, pp:323-328 [Conf]
  109. Shubhankar Basu, Ranga Vemuri
    Process Variation and NBTI Tolerant Standard Cells to Improve Parametric Yield and Lifetime of ICs. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2007, pp:291-298 [Conf]
  110. Angan Das, Ranga Vemuri
    An Automated Passive Analog Circuit Synthesis Framework using Genetic Algorithms. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2007, pp:145-152 [Conf]
  111. Karam S. Chatha, Ranga Vemuri
    Performance Evaluation Tool for Rapid Prototyping of Hardware-Software Codesigns. [Citation Graph (0, 0)][DBLP]
    International Workshop on Rapid System Prototyping, 1998, pp:218-224 [Conf]
  112. Karam S. Chatha, Ranga Vemuri
    An Iterative Algorithm for Partitioning and Scheduling of Area Constrained HW-SW Systems. [Citation Graph (0, 0)][DBLP]
    IEEE International Workshop on Rapid System Prototyping, 1999, pp:134-139 [Conf]
  113. Naren Narasimhan, Ranga Vemuri
    On the Effectiveness of Theorem Proving Guided Discovery of Formal Assertions for a Register Allocator in a High-Level Synthesis System. [Citation Graph (0, 0)][DBLP]
    TPHOLs, 1998, pp:367-386 [Conf]
  114. Glenn Wolfe, Mengmeng Ding, Ranga Vemuri
    Adaptive Sampling and Modeling of Analog Circuit Performance Parameters. [Citation Graph (0, 0)][DBLP]
    VLSI-SOC, 2003, pp:142-0 [Conf]
  115. Hemanth Sampath, Ranga Vemuri
    MSL: A High-Level Language for Parameterized Analog and Mixed Signal Layout Generators. [Citation Graph (0, 0)][DBLP]
    VLSI-SOC, 2003, pp:416-421 [Conf]
  116. Amitava Bhaduri, Ranga Vemuri
    Parasitic Aware Routing Methodology Based on Higher Order RLCK Moment Metrics. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2006, pp:141-146 [Conf]
  117. Ritochit Chakraborty, Mukesh Ranjan, Ranga Vemuri
    Symbolic Time-Domain Behavioral and Performance Modeling of Linear Analog Circuits Using an Efficient Symbolic Newton-Iteration Algorithm for Pole Extraction. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2006, pp:689-694 [Conf]
  118. William L. Bradley, Ranga Vemuri
    Transformations for functional verification of synthesized designs. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1995, pp:243-248 [Conf]
  119. Nagu R. Dhanwada, Adrián Núñez-Aldana, Ranga Vemuri
    Component Characterization and Constraint Transformation Based on Directed Intervals for Analog Synthesis. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1999, pp:589-596 [Conf]
  120. Nagu R. Dhanwada, Ranga Vemuri
    Constraint Allocation in Analog System Synthesis. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1998, pp:253-258 [Conf]
  121. Mengmeng Ding, Ranga Vemuri
    An Active Learning Scheme Using Support Vector Machines for Analog Circuit Feasibility Classification. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2005, pp:528-534 [Conf]
  122. Mengmeng Ding, Ranga Vemuri
    Efficient Analog Performance Macromodeling via Sequential Design Space Decomposition. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2006, pp:553-556 [Conf]
  123. Srinivasan Dasasathyan, Rajesh Radhakrishnan, Ranga Vemuri
    Framework for Synthesis of Virtual Pipelines. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2002, pp:326-331 [Conf]
  124. Sree Ganesan, Ranga Vemuri
    Library Binding for High-Level Synthesis of Analog Systems. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2001, pp:261-268 [Conf]
  125. Sree Ganesan, Ranga Vemuri
    FAAR: A Router for Field-Programmable Analog Arrays. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1999, pp:556-563 [Conf]
  126. Manish Handa, Rajesh Radhakrishnan, Madhubanti Mukherjee, Ranga Vemuri
    A Fast Macro Based Compilation Methodology for Partially Reconfigurable FPGA Designs. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2003, pp:91-0 [Conf]
  127. Abhijit Ghosh, Ranga Vemuri
    Formal Verification of Synthesized Mixed Signal Designs Using *BMDs. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2000, pp:84-0 [Conf]
  128. Sriram Govindarajan, Vinoo Srinivasan, Preetham Lakshmikanthan, Ranga Vemuri
    A Technique for Dynamic High-Level Exploration During Behavioral-Partitioning for Multi-Device Architectures. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2000, pp:212-219 [Conf]
  129. Renqiu Huang, Ranga Vemuri
    On-Line Synthesis for Partially Reconfigurable FPGAs. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2005, pp:663-668 [Conf]
  130. Srinivas Katkoori, Ranga Vemuri, Jay Roy
    A Hierarchical Register Optimization Algorithm for Behavioral Synthesis. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1996, pp:126-132 [Conf]
  131. Xin Jia, Ranga Vemuri
    CAD Tools for a Globally Asynchronous Locally Synchronous FPGA Architecture. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2006, pp:251-256 [Conf]
  132. Madhubanti Mukherjee, Ranga Vemuri
    On Physical-Aware Synthesis of Vertically Integrated 3D Systems. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2005, pp:647-652 [Conf]
  133. Naren Narasimhan, Ranga Vemuri, Jay Roy
    Synchronous Controller Models for Synthesis from Communicating VHDL Processes. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1996, pp:198-204 [Conf]
  134. Vinoo Srinivasan, Ranga Vemuri
    A Retiming Based Relaxation Heuristic for Resource-Constrained Loop Pipelining. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1998, pp:435-441 [Conf]
  135. Sujatha Sundararaman, Sriram Govindarajan, Ranga Vemuri
    Application Specific Macro Based Synthesis. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2001, pp:317-0 [Conf]
  136. Madhavi Vootukuru, Ranga Vemuri, Nand Kumar
    Resource Constrained RTL Partitioning for Synthesis of Multi-FPGA Designs. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1997, pp:140-145 [Conf]
  137. Balasubramanian Sethuraman, Ranga Vemuri
    A Force-directed Approach for Fast Generation of Efficient Multi-Port NoC Architectures. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2007, pp:419-426 [Conf]
  138. Huiying Yang, Ranga Vemuri
    Efficient Symbolic Sensitivity based Parasitic-Inclusive Optimization in Layout Aware Analog Circuit Synthesis. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2007, pp:201-206 [Conf]
  139. Ranga Vemuri, Randolph E. Harr
    Configurable Computing: Technology and Applications - Guest Editors' Introduction. [Citation Graph (0, 0)][DBLP]
    IEEE Computer, 2000, v:33, n:4, pp:39-40 [Journal]
  140. Ranga Vemuri, Nand Kumar, Raghu Vutukuru, Prasad Subba Rao, Praveen Sinha, Ning Ren, Paddy Mamtora, Ram Mandayam, Ram Vemuri, Jayanta Roy
    An Integrated Multicomponent Synthesis for MCMs. [Citation Graph (0, 0)][DBLP]
    IEEE Computer, 1993, v:26, n:4, pp:62-74 [Journal]
  141. Ranga Vemuri, Ram Manday, Vijay Meduri
    Performance Modeling Using PDL. [Citation Graph (0, 0)][DBLP]
    IEEE Computer, 1996, v:29, n:4, pp:44-53 [Journal]
  142. Nand Kumar, Srinivas Katkoori, Leo Rader, Ranga Vemuri
    Profile-Driven Behavioral Synthesis for Low-Power VLSI Systems. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 1995, v:12, n:3, pp:70-84 [Journal]
  143. Jayanta Roy, Nand Kumar, Rajiv Dutta, Ranga Vemuri
    DSS: A Distributed High-Level Synthesis System. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 1992, v:9, n:2, pp:18-32 [Journal]
  144. Nazanin Mansouri, Ranga Vemuri
    Automated Correctness Condition Generation for Formal Verification of Synthesized RTL Designs. [Citation Graph (0, 0)][DBLP]
    Formal Methods in System Design, 2000, v:16, n:1, pp:59-91 [Journal]
  145. Naren Narasimhan, Elena Teica, Rajesh Radhakrishnan, Sriram Govindarajan, Ranga Vemuri
    Theorem Proving Guided Development of Formal Assertions in a Resource-Constrained Scheduler for High-Level Synthesis. [Citation Graph (0, 0)][DBLP]
    Formal Methods in System Design, 2001, v:19, n:3, pp:237-273 [Journal]
  146. Nagu R. Dhanwada, Alex Doboli, Adrián Núñez-Aldana, Ranga Vemuri
    Hierarchical constraint transformation based on genetic optimization for analog system synthesis. [Citation Graph (0, 0)][DBLP]
    Integration, 2006, v:39, n:3, pp:267-290 [Journal]
  147. Alex Doboli, Ranga Vemuri
    Behavioral modeling for high-level synthesis of analog and mixed-signal systems from VHDL-AMS. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:11, pp:1504-1520 [Journal]
  148. Alex Doboli, Ranga Vemuri
    Exploration-based high-level synthesis of linear analog systems operating at low/medium frequencies. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:11, pp:1556-1568 [Journal]
  149. Glenn Wolfe, Ranga Vemuri
    Extraction and use of neural network models in automated synthesis of operational amplifiers. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:2, pp:198-212 [Journal]
  150. Alex Doboli, Nagu R. Dhanwada, Adrián Núñez-Aldana, Ranga Vemuri
    A two-layer library-based approach to synthesis of analog systems from VHDL-AMS specifications. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2004, v:9, n:2, pp:238-271 [Journal]
  151. Ranga Vemuri, Srinivas Katkoori, Meenakshi Kaul, Jay Roy
    An efficient register optimization algorithm for high-level synthesis from hierarchical behavioral specifications. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2002, v:7, n:1, pp:189-216 [Journal]
  152. Balasubramanian Sethuraman, Ranga Vemuri
    Multi2 Router: A Novel Multi Local Port Router Architecture with Broadcast Facility for FPGA-Based Networks-on-Chip. [Citation Graph (0, 0)][DBLP]
    FPL, 2006, pp:1-4 [Conf]
  153. Angan Das, Ranga Vemuri
    GAPSYS: A GA-based Tool for Automated Passive Analog Circuit Synthesis. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:2702-2705 [Conf]
  154. Mukesh Ranjan, Ranga Vemuri
    Exact hierarchical symbolic analysis of large analog networks using a general interconnection template. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]
  155. Raoul F. Badaoui, Ranga Vemuri
    Multi-Placement Structures for Fast and Optimized Placement in Analog Circuit Synthesis [Citation Graph (0, 0)][DBLP]
    CoRR, 2007, v:0, n:, pp:- [Journal]
  156. Jawad Khan, Ranga Vemuri
    An Iterative Algorithm for Battery-Aware Task Scheduling on Portable Computing Platforms [Citation Graph (0, 0)][DBLP]
    CoRR, 2007, v:0, n:, pp:- [Journal]
  157. Karam S. Chatha, Ranga Vemuri
    Hardware-software partitioning and pipelined scheduling of transformative applications. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2002, v:10, n:3, pp:193-208 [Journal]

  158. Topology synthesis of analog circuits based on adaptively generated building blocks. [Citation Graph (, )][DBLP]


  159. Fast Analog Circuit Synthesis Using Sensitivity Based Near Neighbor Searches. [Citation Graph (, )][DBLP]


  160. Cone-based clustering heuristic for list-scheduling algorithms. [Citation Graph (, )][DBLP]


  161. Performance verification using partial evaluation and interval analysis. [Citation Graph (, )][DBLP]


  162. Selective light Vth hopping (SLITH): Bridging the gap between runtime dynamic and leakage. [Citation Graph (, )][DBLP]


  163. A graph grammar based approach to automated multi-objective analog circuit design. [Citation Graph (, )][DBLP]


  164. On the notion of the normal form register-level structures and its applications in design-space exploration. [Citation Graph (, )][DBLP]


  165. A Self-learning Optimization Technique for Topology Design of Computer Networks. [Citation Graph (, )][DBLP]


  166. A layout-aware analog synthesis procedure inclusive of dynamic module geometry selection. [Citation Graph (, )][DBLP]


  167. A methodology for application-specific NoC architecture generation in a dynamic task structure environment. [Citation Graph (, )][DBLP]


  168. Accurate energy breakeven time estimation for run-time power gating. [Citation Graph (, )][DBLP]


  169. Temporal and spatial idleness exploitation for optimal-grained leakage control. [Citation Graph (, )][DBLP]


  170. Power variations of multi-port routers in an application-specific NoC design : A case study. [Citation Graph (, )][DBLP]


  171. Run-time Active Leakage Reduction by power gating and reverse body biasing: An eNERGY vIEW. [Citation Graph (, )][DBLP]


  172. A spline based regression technique on interval valued noisy data. [Citation Graph (, )][DBLP]


  173. ATLAS: An adaptively formed hierarchical cell library based analog synthesis framework. [Citation Graph (, )][DBLP]


  174. Multicasting based topology generation and core mapping for a power efficient networks-on-chip. [Citation Graph (, )][DBLP]


  175. Dynamic virtual ground voltage estimation for power gating. [Citation Graph (, )][DBLP]


  176. Variation Aware Spline Center and Range Modeling for Analog Circuit Performance. [Citation Graph (, )][DBLP]


  177. Power invariant secure IC design methodology using reduced complementary dynamic and differential logic. [Citation Graph (, )][DBLP]


  178. Regression based circuit matrix models for accurate performance estimation of analog circuits. [Citation Graph (, )][DBLP]


  179. On the Use of Hash Tables for Efficient Analog Circuit Synthesis. [Citation Graph (, )][DBLP]


  180. Mismatch Aware Analog Performance Macromodeling Using Spline Center and Range Regression on Adaptive Samples. [Citation Graph (, )][DBLP]


  181. Reduced Complementary Dynamic and Differential Logic: A CMOS Logic Style for DPA-Resistant Secure IC Design. [Citation Graph (, )][DBLP]


  182. Variation-Aware Macromodeling and Synthesis of Analog Circuits Using Spline Center and Range Method and Dynamically Reduced Design Space. [Citation Graph (, )][DBLP]


  183. Fuzzy Logic Based Guidance to Graph Grammar Framework for Automated Analog Circuit Design. [Citation Graph (, )][DBLP]


  184. Efficient Synthesis of a Uniformly Spread Layout Aware Pareto Surface for Analog Circuits. [Citation Graph (, )][DBLP]


  185. Novel Vth Hopping Techniques for Aggressive Runtime Leakage Control. [Citation Graph (, )][DBLP]


  186. Towards a Specification Notation for High-Level Synthesis of Mixed-Signal and Analog Systems. [Citation Graph (, )][DBLP]


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