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Richard B. Brown :
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Claude R. Gauthier , Jayakumaran Sivagnaname , Richard B. Brown Dynamic Receiver Biasing For Inter-Chip Communication. [Citation Graph (0, 0)][DBLP ] ARVLSI, 2001, pp:101-111 [Conf ] Spencer M. Gold , Richard B. Brown , Bruce Bernhardt A Quantitative Approach to Nonlinear Process Design Rule Scaling. [Citation Graph (0, 0)][DBLP ] ARVLSI, 1999, pp:99-113 [Conf ] Matthew R. Guthaus , Dennis Sylvester , Richard B. Brown Process-induced skew reduction in nominal zero-skew clock trees. [Citation Graph (0, 0)][DBLP ] ASP-DAC, 2006, pp:84-89 [Conf ] Michael S. McCorquodale , James L. McCann , Richard B. Brown Newton : a library-based analytical synthesis tool for RF-MEMS resonators. [Citation Graph (0, 0)][DBLP ] ASP-DAC, 2006, pp:279-284 [Conf ] Robert M. Senger , Eric D. Marsman , Michael S. McCorquodale , Richard B. Brown A 16-bit, low-power microsystem with monolithic MEMS-LC clocking. [Citation Graph (0, 0)][DBLP ] ASP-DAC, 2006, pp:94-95 [Conf ] Michael Upton , Thomas Huff , Trevor N. Mudge , Richard B. Brown Resource Allocation in a High Clock Rate Microprocessor. [Citation Graph (0, 0)][DBLP ] ASPLOS, 1994, pp:98-109 [Conf ] Rajiv A. Ravindran , Robert M. Senger , Eric D. Marsman , Ganesh S. Dasika , Matthew R. Guthaus , Scott A. Mahlke , Richard B. Brown Increasing the number of effective registers in a low-power processor using a windowed register file. [Citation Graph (0, 0)][DBLP ] CASES, 2003, pp:125-136 [Conf ] Rajiv A. Ravindran , Pracheeti D. Nagarkar , Ganesh S. Dasika , Eric D. Marsman , Robert M. Senger , Scott A. Mahlke , Richard B. Brown Compiler Managed Dynamic Instruction Placement in a Low-Power Code Cache. [Citation Graph (0, 0)][DBLP ] CGO, 2005, pp:179-190 [Conf ] Ajay Chandna , C. David Kibler , Richard B. Brown , Mark Roberts , Karem A. Sakallah The Aurora RAM Compiler. [Citation Graph (0, 0)][DBLP ] DAC, 1995, pp:261-266 [Conf ] Alan J. Drake , Todd D. Basso , Spencer M. Gold , Keith L. Kraver , Phiroze N. Parakh , Claude R. Gauthier , P. Sean Stetson , Richard B. Brown CGaAs PowerPC FXU. [Citation Graph (0, 0)][DBLP ] DAC, 2000, pp:730-735 [Conf ] Matthew R. Guthaus , Dennis Sylvester , Richard B. Brown Clock buffer and wire sizing using sequential programming. [Citation Graph (0, 0)][DBLP ] DAC, 2006, pp:1041-1046 [Conf ] Phiroze N. Parakh , Richard B. Brown , Karem A. Sakallah Congestion Driven Quadratic Placement. [Citation Graph (0, 0)][DBLP ] DAC, 1998, pp:275-278 [Conf ] Robert M. Senger , Eric D. Marsman , Michael S. McCorquodale , Fadi H. Gebara , Keith L. Kraver , Matthew R. Guthaus , Richard B. Brown A 16-bit mixed-signal microsystem with integrated CMOS-MEMS clock reference. [Citation Graph (0, 0)][DBLP ] DAC, 2003, pp:520-525 [Conf ] Michael S. McCorquodale , Fadi H. Gebara , Keith L. Kraver , Eric D. Marsman , Robert M. Senger , Richard B. Brown A Top-Down Microsystems Design Methodology and Associated Challenges . [Citation Graph (0, 0)][DBLP ] DATE, 2003, pp:20292-20296 [Conf ] Matthew R. Guthaus , Natesan Venkateswaran , Vladimir Zolotov , Dennis Sylvester , Richard B. Brown Optimization objectives and models of variation for statistical gate sizing. [Citation Graph (0, 0)][DBLP ] ACM Great Lakes Symposium on VLSI, 2005, pp:313-316 [Conf ] Rahul M. Rao , Frank Liu , Jeffrey L. Burns , Richard B. Brown A Heuristic to Determine Low Leakage Sleep State Vectors for CMOS Combinational Circuits. [Citation Graph (0, 0)][DBLP ] ICCAD, 2003, pp:689-692 [Conf ] Michael A. Riepe , João P. Marques Silva , Karem A. Sakallah , Richard B. Brown Ravel-XL: A Hardware Accelerator for Assigned-Delay Compiled-Code Logic Gate Simulation. [Citation Graph (0, 0)][DBLP ] ICCD, 1993, pp:361-364 [Conf ] Steven M. Martin , Timothy D. Strong , Richard B. Brown Design, Implementation, and Verification of a CMOS-Integrated Chemical Sensor System. [Citation Graph (0, 0)][DBLP ] ICMENS, 2004, pp:379-385 [Conf ] Kunle Olukotun , Trevor N. Mudge , Richard B. Brown Implementing a Cache for a High-Performance GaAs Microprocessor. [Citation Graph (0, 0)][DBLP ] ISCA, 1991, pp:138-147 [Conf ] Kunle Olukotun , Trevor N. Mudge , Richard B. Brown Performance Optimization of Pipelined Primary Caches. [Citation Graph (0, 0)][DBLP ] ISCA, 1992, pp:181-190 [Conf ] David Nagle , Richard Uhlig , Tim Stanley , Stuart Sechrest , Trevor N. Mudge , Richard B. Brown Design Tradeoffs for Software-Managed TLBs. [Citation Graph (0, 0)][DBLP ] ISCA, 1993, pp:27-38 [Conf ] Michael S. McCorquodale , Mei Kim Ding , Richard B. Brown Study and simulation of CMOS LC oscillator phase noise and jitter. [Citation Graph (0, 0)][DBLP ] ISCAS (1), 2003, pp:665-668 [Conf ] Steven M. Martin , Fadi H. Gebara , Timothy D. Strong , Richard B. Brown A low-voltage, chemical sensor interface for systems-on-chip: the fully-differential potentiostat. [Citation Graph (0, 0)][DBLP ] ISCAS (4), 2004, pp:892-895 [Conf ] Rahul M. Rao , Kanak Agarwal , Dennis Sylvester , Himanshu Kaul , Richard B. Brown , Sani R. Nassif Power-aware global signaling strategies. [Citation Graph (0, 0)][DBLP ] ISCAS (1), 2005, pp:604-607 [Conf ] Koushik K. Das , Rajiv V. Joshi , Ching-Te Chuang , Peter W. Cook , Richard B. Brown New optimal design strategies and analysis of ultra-low leakage circuits for nano-scale SOI technology. [Citation Graph (0, 0)][DBLP ] ISLPED, 2003, pp:168-171 [Conf ] Rahul M. Rao , Kanak Agarwal , Dennis Sylvester , Richard B. Brown , Kevin J. Nowka , Sani R. Nassif Approaches to run-time and standby mode leakage reduction in global buses. [Citation Graph (0, 0)][DBLP ] ISLPED, 2004, pp:188-193 [Conf ] Rahul M. Rao , Jeffrey L. Burns , Anirudh Devgan , Richard B. Brown Efficient techniques for gate leakage estimation. [Citation Graph (0, 0)][DBLP ] ISLPED, 2003, pp:100-103 [Conf ] Harmander Deogun , Robert M. Senger , Dennis Sylvester , Richard B. Brown , Kevin J. Nowka A dual-VDD boosted pulsed bus technique for low power and low leakage operation. [Citation Graph (0, 0)][DBLP ] ISLPED, 2006, pp:73-78 [Conf ] Phiroze N. Parakh , Richard B. Brown Crosstalk constrained global route embedding. [Citation Graph (0, 0)][DBLP ] ISPD, 1999, pp:201-206 [Conf ] Harmander Deogun , Rahul M. Rao , Dennis Sylvester , Richard B. Brown , Kevin J. Nowka Dynamically Pulsed MTCMOS with Bus Encoding for Total Power and Crosstalk Minimization. [Citation Graph (0, 0)][DBLP ] ISQED, 2005, pp:88-93 [Conf ] Jayakumaran Sivagnaname , Hung C. Ngo , Kevin J. Nowka , Robert K. Montoye , Richard B. Brown Controlled-Load Limited Switch Dynamic Logic Circuit. [Citation Graph (0, 0)][DBLP ] ISQED, 2005, pp:83-87 [Conf ] Rahul M. Rao , Kanak Agarwal , Anirudh Devgan , Kevin J. Nowka , Dennis Sylvester , Richard B. Brown Parametric Yield Analysis and Constrained-Based Supply Voltage Optimization. [Citation Graph (0, 0)][DBLP ] ISQED, 2005, pp:284-290 [Conf ] Koushik K. Das , Richard B. Brown Novel Circuit Styles for Minimization of Floating Body Effects in Scaled PD-SOI CMOS. [Citation Graph (0, 0)][DBLP ] ISVLSI, 2003, pp:29-34 [Conf ] Tim Stanley , Michael Upton , Patrick Sherhart , Trevor N. Mudge , Richard B. Brown A microarchitectural performance evaluation of a 3.2 Gbyte/s microprocessor bus. [Citation Graph (0, 0)][DBLP ] MICRO, 1993, pp:31-40 [Conf ] Alan J. Drake , Kevin J. Nowka , Richard B. Brown Evaluation of Dynamic-Threshold Logic for Low-Power VLSI Design in 0.13um PD-SOI. [Citation Graph (0, 0)][DBLP ] VLSI-SOC, 2003, pp:263-0 [Conf ] Michael S. McCorquodale , Eric D. Marsman , Robert M. Senger , Fadi H. Gebara , Richard B. Brown Microsystem and SoC Design with UMIPS. [Citation Graph (0, 0)][DBLP ] VLSI-SOC, 2003, pp:324-0 [Conf ] Koushik K. Das , Richard B. Brown Ultra Low-Leakage Power Strategies for Sub-1 V VLSI: Novel Circuit Styles and Design Methodologies for Partially Depleted Silicon-On-Insulator (PD-SOI) CMOS Technology. [Citation Graph (0, 0)][DBLP ] VLSI Design, 2003, pp:291-296 [Conf ] Rahul M. Rao , Jeffrey L. Burns , Richard B. Brown Analysis and Optimization of Enhanced MTCMOS Scheme. [Citation Graph (0, 0)][DBLP ] VLSI Design, 2004, pp:234-239 [Conf ] Jayakumaran Sivagnaname , Hung C. Ngo , Kevin J. Nowka , Robert K. Montoye , Richard B. Brown Gate-Induced Barrier Field Effect Transistor (GBFET) - A New Thin Film Transistor for Active Matrix Liquid Crystal Display Systems. [Citation Graph (0, 0)][DBLP ] VLSI Design, 2006, pp:89-93 [Conf ] Trevor N. Mudge , Richard B. Brown , William P. Bimingham , Jeffrey A. Dykstra , Ayman I. Kayssi , Ronald J. Lomax , Kunle Olukotun , Karem A. Sakallah , Raymond A. Milano The Design of a Microsupercomputer. [Citation Graph (0, 0)][DBLP ] IEEE Computer, 1991, v:24, n:1, pp:57-64 [Journal ] Kunle Olukotun , Trevor N. Mudge , Richard B. Brown Multilevel Optimization of Pipelined Caches. [Citation Graph (0, 0)][DBLP ] IEEE Trans. Computers, 1997, v:46, n:10, pp:1083-1102 [Journal ] Rajiv A. Ravindran , Robert M. Senger , Eric D. Marsman , Ganesh S. Dasika , Matthew R. Guthaus , Scott A. Mahlke , Richard B. Brown Partitioning Variables across Register Windows to Reduce Spill Code in a Low-Power Processor. [Citation Graph (0, 0)][DBLP ] IEEE Trans. Computers, 2005, v:54, n:8, pp:998-1012 [Journal ] Richard Uhlig , David Nagle , Tim Stanley , Trevor N. Mudge , Stuart Sechrest , Richard B. Brown Design Tradeoffs for Software-Managed TLBs. [Citation Graph (0, 0)][DBLP ] ACM Trans. Comput. Syst., 1994, v:12, n:3, pp:175-205 [Journal ] David Van Campenhout , Hussain Al-Asaad , John P. Hayes , Trevor N. Mudge , Richard B. Brown High-level design verification of microprocessors via error modeling. [Citation Graph (0, 0)][DBLP ] ACM Trans. Design Autom. Electr. Syst., 1998, v:3, n:4, pp:581-599 [Journal ] Eric D. Marsman , Robert M. Senger , G. A. Carichner , S. Kubba , Michael S. McCorquodale , Richard B. Brown DSP architecture for cochlear implants. [Citation Graph (0, 0)][DBLP ] ISCAS, 2006, pp:- [Conf ] Robert M. Senger , Eric D. Marsman , G. A. Carichner , S. Kubba , Michael S. McCorquodale , Richard B. Brown Low-latency, HDL-synthesizable dynamic clock frequency controller with self-referenced hybrid clocking. [Citation Graph (0, 0)][DBLP ] ISCAS, 2006, pp:- [Conf ] Timothy D. Strong , Steven M. Martin , R. F. Franklin , Richard B. Brown Integrated electrochemical neurosensors. [Citation Graph (0, 0)][DBLP ] ISCAS, 2006, pp:- [Conf ] Kanak Agarwal , Rahul M. Rao , Dennis Sylvester , Richard B. Brown Parametric Yield Analysis and Optimization in Leakage Dominated Technologies. [Citation Graph (0, 0)][DBLP ] IEEE Trans. VLSI Syst., 2007, v:15, n:6, pp:613-623 [Journal ] Michael A. Riepe , João P. Marques Silva , Karem A. Sakallah , Richard B. Brown Ravel-XL: a hardware accelerator for assigned-delay compiled-code logic gate simulation. [Citation Graph (0, 0)][DBLP ] IEEE Trans. VLSI Syst., 1996, v:4, n:1, pp:113-129 [Journal ] Richard B. Brown , Bruce Bernhardt , M. LaMacchia , J. Abrokwah , Phiroze N. Parakh , Todd D. Basso , Spencer M. Gold , S. Stetson , Claude R. Gauthier , D. Foster , B. Crawforth , T. McQuire , Karem A. Sakallah , Ronald J. Lomax , Trevor N. Mudge Overview of complementary GaAs technology for high-speed VLSI circuits. [Citation Graph (0, 0)][DBLP ] IEEE Trans. VLSI Syst., 1998, v:6, n:1, pp:47-51 [Journal ] Clock tree synthesis with data-path sensitivity matching. [Citation Graph (, )][DBLP ] A 25MHz all-CMOS reference clock generator for XO-replacement in serial wire interfaces. [Citation Graph (, )][DBLP ] A centralized supply voltage and local body bias-based compensation approach to mitigate within-die process variation. [Citation Graph (, )][DBLP ] On-Chip Process Variation Detection and Compensation Using Delay and Slew-Rate Monitoring Circuits. [Citation Graph (, )][DBLP ] On-Chip Process Variation Detection Using Slew-Rate Monitoring Circuit. [Citation Graph (, )][DBLP ] Analog Circuit Design Methodologies to Improve Negative-Bias Temperature Instability Degradation. [Citation Graph (, )][DBLP ] Search in 0.005secs, Finished in 0.008secs