The SCEAS System
Navigation Menu

Search the dblp DataBase

Title:
Author:

Pinaki Mazumder: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Alejandro F. González, Pinaki Mazumder
    Compact Signed-Digit Adder Using Multiple-Valued Logic. [Citation Graph (0, 0)][DBLP]
    ARVLSI, 1997, pp:96-113 [Conf]
  2. Woo Hyung Lee, Pinaki Mazumder
    Parallel Processing Based Power Reduction in a 256 State Viterbi Decoder. [Citation Graph (0, 0)][DBLP]
    ASAP, 2006, pp:182-185 [Conf]
  3. Qinwei Xu, Pinaki Mazumder
    Rational ABCD Modeling of High-Speed Interconnects. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2002, pp:147-154 [Conf]
  4. Baohua Wang, Pinaki Mazumder
    Optimization of circuit trajectories: an auxiliary network approach. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2006, pp:416-421 [Conf]
  5. Qinwei Xu, Pinaki Mazumder
    Efficient Macromodeling for On-Chip Interconnects. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2002, pp:561-566 [Conf]
  6. Li Ding 0002, Pinaki Mazumder
    A novel technique to improve noise immunity of CMOS dynamic logic circuits. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:900-903 [Conf]
  7. Pinaki Mazumder, Janak H. Patel, W. Kent Fuchs
    Design and Algorithms for Parallel Testing of Random Access and Content Addressable Memories. [Citation Graph (0, 0)][DBLP]
    DAC, 1987, pp:689-694 [Conf]
  8. Jih-Shyr Yih, Pinaki Mazumder
    A Neural Network Design for Circuit Partitioning. [Citation Graph (0, 0)][DBLP]
    DAC, 1989, pp:406-411 [Conf]
  9. Kanad Chakraborty, Anurag Gupta, Mayukh Bhattacharya, Shriram Kulkarni, Pinaki Mazumder
    A Physical Design Tool for Built-in Self-Repairable Static RAMs. [Citation Graph (0, 0)][DBLP]
    DATE, 1999, pp:714-0 [Conf]
  10. Qinwei Xu, Pinaki Mazumder
    Efficient and passive modeling of transmission lines by using differential quadrature method. [Citation Graph (0, 0)][DBLP]
    DATE, 2001, pp:437-444 [Conf]
  11. Qinwei Xu, Pinaki Mazumder
    Formulation of Low-Order Dominant Poles for Y-Matrix of Interconnects. [Citation Graph (0, 0)][DBLP]
    DATE, 2002, pp:820-825 [Conf]
  12. Li Ding 0002, Pinaki Mazumder
    Optimal Transistor Tapering for High-Speed CMOS Circuits. [Citation Graph (0, 0)][DBLP]
    DATE, 2002, pp:708-715 [Conf]
  13. Li Ding 0002, Pinaki Mazumder
    Accurate Estimating Simultaneous Switching Noises by Using Application Specific Device Modeling. [Citation Graph (0, 0)][DBLP]
    DATE, 2002, pp:1038-1043 [Conf]
  14. Li Ding 0002, Pinaki Mazumder
    Modeling Noise Transfer Characteristic of Dynamic Logic Gates. [Citation Graph (0, 0)][DBLP]
    DATE, 2003, pp:11114-11117 [Conf]
  15. Baohua Wang, Pinaki Mazumder
    EM Wave Coupling Noise Modeling Based on Chebyshev Approximation and Exact Moment Formulation. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:976-981 [Conf]
  16. Baohua Wang, Pinaki Mazumder
    A logarithmic full-chip thermal analysis algorithm based on multi-layer Green's function. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:39-44 [Conf]
  17. Anurag Gupta, Kanad Chakraborty, Pinaki Mazumder
    A Silicon Compiler for Fault-Tolerant ROMs. [Citation Graph (0, 0)][DBLP]
    DFT, 1998, pp:270-275 [Conf]
  18. Henrik Esbensen, Pinaki Mazumder
    A Genetic Algorithm for the Steiner Problem in a Graph. [Citation Graph (0, 0)][DBLP]
    EDAC-ETC-EUROASIC, 1994, pp:402-406 [Conf]
  19. Heming Chan, Pinaki Mazumder
    A Systolic Architecture for High Speed Hypergraph Partitioning Using a Genetic Algorithm. [Citation Graph (0, 0)][DBLP]
    Evo Workshops, 1994, pp:109-126 [Conf]
  20. Mayukh Bhattacharya, Pinaki Mazumder
    Noise Margins of Threshold Logic Gates containing Resonant Tunneling Diodes. [Citation Graph (0, 0)][DBLP]
    Great Lakes Symposium on VLSI, 1998, pp:65-70 [Conf]
  21. Patrick Fay, Gary H. Bernstein, David H. Chow, J. Schulman, Pinaki Mazumder, W. Williamson, B. K. Gilbert
    Integration of InAs/AlSb/GaSb Resonant Interband Tunneling Diodes with Heterostructure Field-Effect Transistors for Ultra-High-Speed Digital Circuit Applications. [Citation Graph (0, 0)][DBLP]
    Great Lakes Symposium on VLSI, 1999, pp:162-165 [Conf]
  22. Qinwei Xu, Pinaki Mazumder
    Novel interconnect modeling by using high-order compact finite difference methods. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2002, pp:148-152 [Conf]
  23. Qinwei Xu, Pinaki Mazumder
    Modeling of transmission lines with EM wave coupling by the finite difference quadrature method. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2004, pp:25-28 [Conf]
  24. Tetsuya Uemura, Pinaki Mazumder
    Design and Analysis of a Novel Quantum-MOS Sense Amplifier Circuit. [Citation Graph (0, 0)][DBLP]
    Great Lakes Symposium on VLSI, 1999, pp:158-161 [Conf]
  25. Kanad Chakraborty, Pinaki Mazumder
    An efficient, bus-layout based method for early diagnosis of bussed driver shorts in printed circuit boards. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1996, pp:685-688 [Conf]
  26. Li Ding 0002, David Blaauw, Pinaki Mazumder
    Efficient crosstalk noise modeling using aggressor and tree reductions. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2002, pp:595-600 [Conf]
  27. Pinaki Mazumder
    Evaluation of Three Interconnection Networks for CMOS VLSI Implementation. [Citation Graph (0, 0)][DBLP]
    ICPP, 1986, pp:200-207 [Conf]
  28. R. B. Panwar, Pinaki Mazumder
    A Parallel Karmarkar Algorithm on Orthogonal Tree Networks. [Citation Graph (0, 0)][DBLP]
    ICPP (3), 1990, pp:274-277 [Conf]
  29. Sing-Rong Li, Pinaki Mazumder, Leon O. Chua
    On the implementation of RTD based CNNs. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2004, pp:25-28 [Conf]
  30. Sing-Rong Li, Pinaki Mazumder, Kyounghoon Yang
    On the functional failure and switching time analysis of the MOBILE circuit [monostable-bistable logic element]. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2005, pp:2531-2534 [Conf]
  31. Qinwei Xu, Pinaki Mazumder
    Efficient interconnect modeling by Finite Difference Quadrature methods. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2003, pp:592-595 [Conf]
  32. Baohua Wang, Pinaki Mazumder
    Subgridding method for speeding up FD-TLM circuit simulation. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2003, pp:20-23 [Conf]
  33. Baohua Wang, Pinaki Mazumder
    Integrating lumped networks into full wave TLM/FDTD methods using passive discrete circuit models. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2005, pp:1948-1951 [Conf]
  34. Hui Zhang, Pinaki Mazumder
    Design of a new sense amplifier flip-flop with improved power-delay-product. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2005, pp:1262-1265 [Conf]
  35. Hui Zhang, Pinaki Mazumder, Li Ding 0002, Kyounghoon Yang
    Performance modeling of resonant tunneling based RAMs. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2003, pp:900-903 [Conf]
  36. Hui Zhang, Pinaki Mazumder, Kyounghoon Yang
    Resonant tunnelling diode based QMOS edge triggered flip-flop design. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2004, pp:705-708 [Conf]
  37. Li Ding 0002, Pinaki Mazumder, N. Srinivas
    A dual-rail static edge-triggered latch. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2001, pp:645-648 [Conf]
  38. Baohua Wang, Pinaki Mazumder
    Fast thermal analysis for VLSI circuits via semi-analytical Green's function in multi-layer materials. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2004, pp:409-412 [Conf]
  39. Qinwei Xu, Pinaki Mazumder, Li Ding 0002
    Novel macromodeling for on-chip RC/RLC interconnects. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2002, pp:189-192 [Conf]
  40. Li Ding 0002, Pinaki Mazumder
    Modified long channel model for analytical study of DSM circuits. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2002, pp:541-544 [Conf]
  41. Tetsuya Uemura, Pinaki Mazumder
    Rise time analysis of MOBILE circuit. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2002, pp:864-867 [Conf]
  42. Li Ding 0002, Pinaki Mazumder, David Blaauw
    Crosstalk noise estimation using effective coupling capacitance. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2002, pp:645-648 [Conf]
  43. Baohua Wang, Pinaki Mazumder
    On optimality of adiabatic switching in MOS energy-recovery circuit. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2004, pp:236-239 [Conf]
  44. Baohua Wang, Pinaki Mazumder
    On optimality of adiabatic switching in MOS energy-recovery circuit. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2004, pp:332-337 [Conf]
  45. Alejandro F. González, Mayukh Bhattacharya, Shriram Kulkarni, Pinaki Mazumder
    Standard CMOS Implementation of a Multiple-Valued Logic Signed-Digit Adder Based on Negative Differential-Resistance Devices. [Citation Graph (0, 0)][DBLP]
    ISMVL, 2000, pp:323-0 [Conf]
  46. Pinaki Mazumder
    An On-Chip Double-Bit Error-Correcting Code for Three-Dimensional Dynamic Random-Access Memory. [Citation Graph (0, 0)][DBLP]
    ITC, 1988, pp:279-288 [Conf]
  47. Pinaki Mazumder
    An Integrated Built-In Self-Testing and Self-Repair of VLSI/WSI Hexagonal Arrays. [Citation Graph (0, 0)][DBLP]
    ITC, 1992, pp:968-977 [Conf]
  48. Sundarar Mohan, Pinaki Mazumder
    Fault Modeling and Testing of GaAs Static Random Access Memories. [Citation Graph (0, 0)][DBLP]
    ITC, 1991, pp:665-674 [Conf]
  49. Mayukh Bhattacharya, Pinaki Mazumder
    Convergence Issues in Resonant Tunneling Diode Circuit Simulation. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2000, pp:499-0 [Conf]
  50. Mayukh Bhattacharya, Pinaki Mazumder, Ronald J. Lomax
    Fd-Tlm Electromagnetic Field Simulation Of High-Speed Iii-V Heterojunction Bipolar Transistor Digital Logic Gates. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2001, pp:470-474 [Conf]
  51. Li Ding 0002, Pinaki Mazumder
    The Impact of Bit-Line Coupling and Ground Bounce on CMOS SRAM Performance. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2003, pp:234-0 [Conf]
  52. Li Ding 0002, Pinaki Mazumder
    Dynamic Noise Margin: Definitions and Model. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2004, pp:1001-0 [Conf]
  53. Henrik Esbensen, Pinaki Mazumder
    SAGA: A Unification of the Genetic Algorithm with Simulated Annealing and its Application to Macro-Cell Placement. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1994, pp:211-214 [Conf]
  54. Alejandro F. González, Pinaki Mazumder
    Comparison of Bistable Circuits Based on Resonant-Tunneling Diodes. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2003, pp:493-492 [Conf]
  55. Shriram Kulkarni, Pinaki Mazumder, George I. Haddad
    A high-speed 32-bit parallel correlator for spread spectrum communication. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1996, pp:313-315 [Conf]
  56. Qinwei Xu, Pinaki Mazumder
    Rational ABCD Modeling of High-Speed Interconnects. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2002, pp:147-0 [Conf]
  57. Pinaki Mazumder, Shriram Kulkarni, Mayukh Bhattacharya, Alejandro F. González
    Circuit Design using Resonant Tunneling Diodes. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1998, pp:501-506 [Conf]
  58. Khushro Shahookar, W. Khamisani, Pinaki Mazumder, Sudhakar M. Reddy
    Genetic Beam Search for Gate Matrix Layout. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1993, pp:208-213 [Conf]
  59. Khushro Shahookar, Pinaki Mazumder
    Genetic multiway partitioning. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1995, pp:365-369 [Conf]
  60. Baohua Wang, Pinaki Mazumder
    Multivariate Normal Distribution Based Statistical Timing Analysis Using Global Projection and Local Expansion. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2005, pp:380-385 [Conf]
  61. Baohua Wang, Pinaki Mazumder
    Bounding Supply Noise Induced Path Delay Variation Using a Relaxation Approach. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2006, pp:349-354 [Conf]
  62. Qinwei Xu, Pinaki Mazumder
    Efficient Macromodeling for On-Chip Interconnects. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2002, pp:561-566 [Conf]
  63. Qinwei Xu, Pinaki Mazumder, Mayukh Bhattacharya
    Modeling of Nonuniform Interconnects by Using Differential Quadrature Method. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2001, pp:327-332 [Conf]
  64. Qinwei Xu, Pinaki Mazumder, Zheng-Fan Li
    Transmission Line Modeling by Modified Method of Characteristics. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2001, pp:359-364 [Conf]
  65. Pinaki Mazumder
    Analysis of Failures in Deep Submicron SRAM Cells. [Citation Graph (0, 0)][DBLP]
    VTS, 1998, pp:184-187 [Conf]
  66. Khushro Shahookar, Pinaki Mazumder
    VLSI Cell Placement Techniques. [Citation Graph (0, 0)][DBLP]
    ACM Comput. Surv., 1991, v:23, n:2, pp:143-220 [Journal]
  67. Pinaki Mazumder
    Planar decomposition for quadtree data structure. [Citation Graph (0, 0)][DBLP]
    Computer Vision, Graphics, and Image Processing, 1987, v:38, n:3, pp:258-274 [Journal]
  68. Pinaki Mazumder, John P. Hayes
    Guest Editor's Introduction: Testing and Improving the Testability of Multimegabit Memories. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 1993, v:10, n:1, pp:6-7 [Journal]
  69. Anurag Gupta, Kanad Chakraborty, Pinaki Mazumder
    FTROM: A Silicon Compiler for Fault-tolerant ROMs. [Citation Graph (0, 0)][DBLP]
    Integration, 1998, v:26, n:1-2, pp:117-140 [Journal]
  70. Alejandro F. González, Pinaki Mazumder
    Redundant arithmetic, algorithms and implementations. [Citation Graph (0, 0)][DBLP]
    Integration, 2000, v:30, n:1, pp:13-53 [Journal]
  71. Alejandro F. González, Pinaki Mazumder
    Multiple-Valued Signed-Digit Adder Using Negative Differential-Resistance Devices. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1998, v:47, n:9, pp:947-959 [Journal]
  72. Pinaki Mazumder
    Evaluation of On-Chip Static Interconnection Networks. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1987, v:36, n:3, pp:365-369 [Journal]
  73. Pinaki Mazumder
    Design of a Fault-Tolerant Three-Dimensional Dynamic Random-Access Memory with On-Chip Error-Correcting Circuit. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1993, v:42, n:12, pp:1453-1468 [Journal]
  74. Pinaki Mazumder, Janak H. Patel
    Parallel Testing for Pattern-Sensitive Faults in Semiconductor Random-Access Memories. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1989, v:38, n:3, pp:394-407 [Journal]
  75. Michael D. Smith, Pinaki Mazumder
    Generation of Minimal Vertex Covers for Row/Column Allocation in Self-Repairable Arrays. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1996, v:45, n:1, pp:109-115 [Journal]
  76. Mayukh Bhattacharya, Pinaki Mazumder
    Augmentation of SPICE for simulation of circuits containingresonant tunneling diodes. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2001, v:20, n:1, pp:39-50 [Journal]
  77. Li Ding 0002, David T. Blaauw, Pinaki Mazumder
    Accurate crosstalk noise modeling for early signal integrity analysis. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:5, pp:627-634 [Journal]
  78. Pinaki Mazumder, Janak H. Patel, W. Kent Fuchs
    Methodologies for testing embedded content addressable memories. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1988, v:7, n:1, pp:11-20 [Journal]
  79. Pinaki Mazumder, Jih-Shyr Yih
    A new built-in self-repair approach to VLSI memory yield enhancement by using neural-type circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1993, v:12, n:1, pp:124-136 [Journal]
  80. Pinaki Mazumder, Jih-Shyr Yih
    Restructuring of square processor arrays by built-in self-repair circuit. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1993, v:12, n:9, pp:1255-1265 [Journal]
  81. Sundarar Mohan, Pinaki Mazumder
    Wolverines: standard cell placement on a network of workstations. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1993, v:12, n:9, pp:1312-1326 [Journal]
  82. Sundarar Mohan, Pinaki Mazumder
    Analytical and simulation studies of failure modes in SRAMs using high electron mobility transistors. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1993, v:12, n:12, pp:1885-1896 [Journal]
  83. Sundarar Mohan, Jian Ping Sun, Pinaki Mazumder, George I. Haddad
    Device and circuit simulation of quantum electronic devices. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1995, v:14, n:6, pp:653-662 [Journal]
  84. Khushro Shahookar, Pinaki Mazumder
    A genetic approach to standard cell placement using meta-genetic parameter optimization. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1990, v:9, n:5, pp:500-511 [Journal]
  85. Raja Venkateswaran, Pinaki Mazumder
    A hexagonal array machine for multilayer wire routing. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1990, v:9, n:10, pp:1096-1112 [Journal]
  86. Raja Venkateswaran, Pinaki Mazumder, K. G. Shin
    Restructuring WSI hexagonal processor arrays. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1992, v:11, n:12, pp:1574-1585 [Journal]
  87. Jih-Shyr Yih, Pinaki Mazumder
    A neural network design for circuit partitioning. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1990, v:9, n:12, pp:1265-1271 [Journal]
  88. Li Ding 0002, Pinaki Mazumder
    On circuit techniques to improve noise immunity of CMOS dynamic logic. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2004, v:12, n:9, pp:910-925 [Journal]
  89. Raja Venkateswaran, Pinaki Mazumder
    Coprocessor design for multilayer surface-mounted PCB routing. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1993, v:1, n:1, pp:31-45 [Journal]
  90. Pinaki Mazumder
    Guest Editorial Special Section On Impacts Of Emerging Technologies On VLSI Systems. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1998, v:6, n:1, pp:4-5 [Journal]
  91. Kanad Chakraborty, Shriram Kulkarni, Mayukh Bhattacharya, Pinaki Mazumder, Anurag Gupta
    A physical design tool for built-in self-repairable RAMs. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2001, v:9, n:2, pp:352-364 [Journal]
  92. Li Ding 0002, Pinaki Mazumder
    Simultaneous switching noise analysis using application specific device modeling. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2003, v:11, n:6, pp:1146-1152 [Journal]
  93. Qinwei Xu, Pinaki Mazumder
    Equivalent-circuit interconnect modeling based on the fifth-order differential quadrature methods. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2003, v:11, n:6, pp:1068-1079 [Journal]

  94. A programmable boundary scan technique for board-level, parallel functional duplex march testing of word-oriented multiport static RAMs. [Citation Graph (, )][DBLP]


  95. An accurate interconnect thermal model using equivalent transmission line circuit. [Citation Graph (, )][DBLP]


  96. GASP: a Genetic Algorithm for Standard cell Placement. [Citation Graph (, )][DBLP]


  97. Disruptive technologies and neurally-inspired architectures. [Citation Graph (, )][DBLP]


Search in 0.011secs, Finished in 0.018secs
NOTICE1
System may not be available sometimes or not working properly, since it is still in development with continuous upgrades
NOTICE2
The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP
 
System created by asidirop@csd.auth.gr [http://users.auth.gr/~asidirop/] © 2002
for Data Engineering Laboratory, Department of Informatics, Aristotle University © 2002