The SCEAS System
Navigation Menu
Introduction
Collection Based
Clustering
Ranking
Paper Based
Journals
Conferences
DB Status
Statistics
Search

Search the dblp DataBase

Title:
Author:
Paul E. Hasler: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Paul E. Hasler, Bradley A. Minch, Chris Diorio
    Adaptive Circuits Using pFET Floating-Gate Devices. [Citation Graph (0, 0)][DBLP]
    ARVLSI, 1999, pp:215-231 [Conf]
  2. Matt Kucic, Paul E. Hasler, Jeff Dugger, David V. Anderson
    Programmable and Adaptive Analog Filters using Arrays of Floating-Gate Circuits. [Citation Graph (0, 0)][DBLP]
    ARVLSI, 2001, pp:148-162 [Conf]
  3. Tyson S. Hall, Paul E. Hasler, David V. Anderson
    Field-Programmable Analog Arrays: A Floating-Gate Approach. [Citation Graph (0, 0)][DBLP]
    FPL, 2002, pp:424-433 [Conf]
  4. Tyson S. Hall, Christopher M. Twigg, Paul E. Hasler, David V. Anderson
    Developing Large-Scale Field-Programmable Analog Arrays. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2004, pp:- [Conf]
  5. David N. Abramson, Jordan D. Gray, Christopher M. Twigg, Paul E. Hasler
    Characteristics and programming of floating-gate pFET switches in an FPAA crossbar network. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2005, pp:468-471 [Conf]
  6. Daniel J. Allen, Angelo W. Pereira, Paul E. Hasler
    A programmable coefficient continuous-time A/D Delta-Sigma modulator. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2004, pp:1148-1151 [Conf]
  7. Abhishek Bandyopadhyay, Jungwon Lee, Ryan W. Robucci, Paul E. Hasler
    A 80µW/frame 104×128 CMOS imager front end for JPEG compression. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2005, pp:5318-5321 [Conf]
  8. Abhishek Bandyopadhyay, Guillermo J. Serrano, Paul E. Hasler
    Programming analog computational memory elements to 0.2% accuracy over 3.5 decades using a predictive method. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2005, pp:2148-2151 [Conf]
  9. Philomena C. Brady, Paul E. Hasler
    Offset compensation in flash ADCs using floating-gate circuits. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 2005, pp:6154-6157 [Conf]
  10. Ravi Chawla, Haw-Jing Lo, Arindam Basu, Paul E. Hasler, Bradley A. Minch
    A fully programmable log-domain bandpass filter using multiple-input translinear elements. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2004, pp:33-36 [Conf]
  11. Ravi Chawla, Guillermo J. Serrano, Daniel J. Allen, Angelo W. Pereira, Paul E. Hasler
    Fully differential floating-gate programmable OTAs with novel common-mode feedback. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2004, pp:817-820 [Conf]
  12. Ravi Chawla, Christopher M. Twigg, Paul E. Hasler
    An analog modulator/demodulator using a programmable arbitrary waveform generator. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 2005, pp:6106-6109 [Conf]
  13. Brian P. Degnan, Richard B. Wunderlich, Paul E. Hasler
    Programmable floating-gate techniques for CMOS inverters. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2005, pp:2441-2444 [Conf]
  14. Chris Diorio, Sunit Mahajan, Paul E. Hasler, Bradley A. Minch, Carver Mead
    A High-Resolution Non-Volatile Analog Memory Cell. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1995, pp:2233-2236 [Conf]
  15. Jeff Dugger, Paul E. Hasler
    Supervised learning in a two-input analog floating-gate node. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2004, pp:756-759 [Conf]
  16. Ethan Farquhar, David N. Abramson, Paul E. Hasler
    A reconfigurable bidirectional active 2 dimensional dendrite model. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2004, pp:313-316 [Conf]
  17. Ethan Farquhar, Paul E. Hasler
    A bio-physically inspired silicon neuron. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2004, pp:309-312 [Conf]
  18. Christal Gordon, Ethan Farquhar, Paul E. Hasler
    A family of floating-gate adapting synapses based upon transistor channel models. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2004, pp:317-20 [Conf]
  19. David W. Graham, Ethan Farquhar, Brian P. Degnan, Christal Gordon, Paul E. Hasler
    Indirect programming of floating-gate transistors. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2005, pp:2172-2175 [Conf]
  20. David W. Graham, Paul D. Smith, Richard Ellis, Ravi Chawla, Paul E. Hasler
    A programmable bandpass array using floating-gate elements. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2004, pp:97-100 [Conf]
  21. David W. Graham, Paul D. Smith, Richard Ellis, Ravi Chawla, Paul E. Hasler
    A low-power, programmable bandpass filter section for higher-order filter-bank applications. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2005, pp:1980-1983 [Conf]
  22. Paul E. Hasler, Chris Diorio, Bradley A. Minch, Carver Mead
    Single Transistor Learning Synapse with Long Term Storage. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1995, pp:1660-1663 [Conf]
  23. Mark Hooper, Matt Kucic, Paul E. Hasler
    5V-only, standard 0.5/spl mu/m CMOS programmable and adaptive floating-gate circuits and arrays using CMOS charge pumps. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2004, pp:832-835 [Conf]
  24. Mark Hooper, Matt Kucic, Paul E. Hasler
    Characterization of charge-pump rectifiers for standard submicron CMOS processes. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2004, pp:964-967 [Conf]
  25. Mark Hooper, Matt Kucic, Paul E. Hasler
    Integration of high voltage charge-pumps in a submicron standard CMOS process for programming analog floating-gate circuits. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2005, pp:125-128 [Conf]
  26. Haw-Jing Lo, Guillermo J. Serrano, Paul E. Hasler, David V. Anderson, Bradley A. Minch
    Programmable multiple input translinear elements. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2004, pp:757-760 [Conf]
  27. Bradley A. Minch, Chris Diorio, Paul E. Hasler, Carver Mead
    A vMOS Soft-Maximum Current Mirror. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1995, pp:2249-2252 [Conf]
  28. Erhan Ozalevli, Paul E. Hasler
    Programmable floating-gate CMOS resistors. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2005, pp:2168-2171 [Conf]
  29. Erhan Ozalevli, Paul E. Hasler, Farhan Adil
    Programmable voltage-output, floating-gate digital-analog converter. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2004, pp:1064-1067 [Conf]
  30. Erhan Ozalevli, Christopher M. Twigg, Paul E. Hasler
    10-bit programmable voltage-output digital-analog converter. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 2005, pp:5553-5556 [Conf]
  31. Sheng-Yu Peng, Bradley A. Minch, Paul E. Hasler
    A programmable floating-gate bump circuit with variable width. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2005, pp:4341-4344 [Conf]
  32. Angelo W. Pereira, Daniel J. Allen, Paul E. Hasler
    A 0.5µm CMOS programmable discrete-time Delta-Sigma modulator with floating gate elements. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2004, pp:213-216 [Conf]
  33. Guillermo J. Serrano, Paul E. Hasler
    A floating-gate DAC array. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2004, pp:357-360 [Conf]
  34. Guillermo J. Serrano, Paul D. Smith, Haw-Jing Lo, Ravi Chawla, Tyson S. Hall, Christopher M. Twigg, Paul E. Hasler
    Automatic rapid programming of large arrays of floating-gate elements. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2004, pp:373-376 [Conf]
  35. Paul D. Smith, David D. Graham, Ravi Chawla, Paul E. Hasler
    A five-transistor bandpass filter element. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2004, pp:861-864 [Conf]
  36. Venkatesh Srinivasan, Jeff Dugger, Paul E. Hasler
    An adaptive analog synapse circuit that implements the least-mean-square learning rule. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2005, pp:4441-4444 [Conf]
  37. Shyam Subramanian, David V. Anderson, Paul E. Hasler
    Synthesis of static multiple input multiple output MITE networks. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2004, pp:189-192 [Conf]
  38. Shyam Subramanian, David V. Anderson, Paul E. Hasler, Bradley A. Minch
    Synthesis of MITE log-domain filters with unique operating points. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2005, pp:996-999 [Conf]
  39. Heejong Yoo, David Graham, David V. Anderson, Paul E. Hasler
    C4 band-pass delay filter for continuous-time subband adaptive tapped-delay filter. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2004, pp:792-795 [Conf]
  40. Paul E. Hasler, Bradley A. Minch, Chris Diorio
    Floating-gate devices: they are not just for digital memories any more. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 1999, pp:388-391 [Conf]
  41. Paul E. Hasler, Paul D. Smith
    An autozeroing floating-gate amplifier with gain adaptation. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 1999, pp:412-415 [Conf]
  42. Bradley A. Minch, Paul E. Hasler
    A floating-gate technology for digital CMOS processes. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 1999, pp:400-403 [Conf]
  43. Bradley A. Minch, Paul E. Hasler, Chris Diorio
    Synthesis of multiple-input translinear element networks. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 1999, pp:236-239 [Conf]
  44. Paul E. Hasler, Jeff Dugger
    Correlation learning rule in floating-gate pFET synapses. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 1999, pp:387-390 [Conf]
  45. Tyson S. Hall, Christopher M. Twigg, Paul E. Hasler, David V. Anderson
    Application performance of elements in a floating-gate FPAA. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2004, pp:589-592 [Conf]
  46. Paul E. Hasler, Abhishek Bandyopadhyay, Paul D. Smith
    A matrix transform imager allowing high-fill factor. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2002, pp:337-340 [Conf]
  47. R. A. Blum, Charles S. Wilson, Paul E. Hasler, Stephen P. DeWeerth
    A CMOS imager with real-time frame differencing and centroid computation. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2002, pp:329-332 [Conf]
  48. Joseph D. Neff, Brian K. Meadows, Edgar A. Brown, Stephen P. DeWeerth, Paul E. Hasler
    A CMOS coupled nonlinear oscillator array. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2002, pp:301-304 [Conf]
  49. Paul D. Smith, Matt Kucic, Richard Ellis, Paul E. Hasler, David V. Anderson
    Mel-frequency cepstrum encoding in analog floating-gate circuitry. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2002, pp:671-674 [Conf]
  50. J. A. Bragg, Edgar A. Brown, Paul E. Hasler, Stephen P. DeWeerth
    A silicon model of an adapting motoneuron. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2002, pp:261-264 [Conf]
  51. C. Duffy, Ethan Farquhar, Paul E. Hasler
    Practical issues using e-pot circuits. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2002, pp:493-496 [Conf]
  52. Christal Gordon, Paul E. Hasler
    Biological learning modeled in an adaptive floating-gate system. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2002, pp:609-612 [Conf]
  53. Paul D. Smith, Matt Kucic, Paul E. Hasler
    Accurate programming of analog floating-gate arrays. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2002, pp:489-492 [Conf]
  54. T. M. Massengill, D. M. Wilson, Paul E. Hasler, David W. Graham
    Empirical comparison of analog and digital auditory preprocessing for automatic speech recognition. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2002, pp:77-80 [Conf]
  55. David N. Abramson, Jordan D. Gray, Shyam Subramanian, Paul E. Hasler
    A Field-Programmable Analog Array Using Translinear Elements. [Citation Graph (0, 0)][DBLP]
    IWSOC, 2005, pp:425-428 [Conf]
  56. Paul E. Hasler
    Low-Power Programmable Signal Processing, invited. [Citation Graph (0, 0)][DBLP]
    IWSOC, 2005, pp:413-418 [Conf]
  57. Paul E. Hasler
    Floating-Gate Devices, Circuits, and Systems, invited. [Citation Graph (0, 0)][DBLP]
    IWSOC, 2005, pp:482-487 [Conf]
  58. Paul Hasler, AiChen Low
    Programmable Low Dropout Voltage Regulator. [Citation Graph (0, 0)][DBLP]
    IWSOC, 2005, pp:459-462 [Conf]
  59. Paul E. Hasler, Chris Diorio, Bradley A. Minch, Carver Mead
    Single Transistor Learning Synapses. [Citation Graph (0, 0)][DBLP]
    NIPS, 1994, pp:817-824 [Conf]
  60. W. Fritz Kruger, Paul E. Hasler, Bradley A. Minch, Christof Koch
    An Adaptive WTA using Floating Gate Technology. [Citation Graph (0, 0)][DBLP]
    NIPS, 1996, pp:720-726 [Conf]
  61. Bradley A. Minch, Paul E. Hasler, Chris Diorio, Carver Mead
    A Silicon Axon. [Citation Graph (0, 0)][DBLP]
    NIPS, 1994, pp:739-746 [Conf]
  62. Arindam Basu, Ryan W. Robucci, Paul E. Hasler
    A Low-Power, Compact, Adaptive Logarithmic Transimpedance Amplifier Operating over Seven Decades of Current. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:3055-3058 [Conf]
  63. Kofi M. Odame, Christopher M. Twigg, Arindam Basu, Paul E. Hasler
    Studying Nonlinear Dynamical Systems on a Reconfigurable Analog Platform. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:445-448 [Conf]
  64. Kofi M. Odame, Paul E. Hasler
    An Adaptive Quality-Factor Bandpass Filter. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:3295-3298 [Conf]
  65. Christopher M. Twigg, Jordan D. Gray, Paul E. Hasler
    Programmable Floating Gate FPAA Switches Are Not Dead Weight. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:169-172 [Conf]
  66. Paul E. Hasler, Scott Kozoil, Ethan Farquhar, Arindam Basu
    Transistor Channel Dendrites implementing HMM classifiers. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:3359-3362 [Conf]
  67. Arindam Basu, Paul E. Hasler
    A Fully Integrated Architecture for Fast Programming of Floating Gates. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:957-960 [Conf]
  68. Christopher M. Twigg, Paul E. Hasler
    Programmable Conductance Switches for FPAAs. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:173-176 [Conf]
  69. Arindam Basu, Kofi M. Odame, Paul E. Hasler
    Dynamics of a Logarithmic Transimpedance Amplifier. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:1673-1676 [Conf]
  70. Shyam Subramanian, David V. Anderson, Paul E. Hasler, Bradley A. Minch
    Optimal Synthesis of MITE Translinear Loops. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:2822-2825 [Conf]
  71. Richard B. Wunderlich, Brian P. Degnan, Paul E. Hasler
    Capacitively-Biased Floating-Gate CMOS: a New Logic Family. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:3728-3731 [Conf]
  72. David W. Graham, Paul E. Hasler
    Run-Time Programming of Analog Circuits Using Floating-Gate Transistors. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:3816-3819 [Conf]
  73. Paul E. Hasler, Arindam Basu, Sctt Kozil
    Above Threshold pFET InjectionModeling intended for ProgrammingFloating-Gate Systems. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:1557-1560 [Conf]
  74. Kofi M. Odame, Paul E. Hasler
    An Efficient Oscillator Design Based on OTA Nonlinearity. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:921-924 [Conf]
  75. Christopher M. Twigg, Paul E. Hasler, I. Faik Baskaya
    A Self-Contained Large-Scale FPAA Development Platform. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:1187-1191 [Conf]
  76. Paul E. Hasler, Christopher M. Twigg
    An OTA-based Large-Scale Field Programmable Analog Array (FPAA) for faster On-Chip Communication and Computation. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:177-180 [Conf]
  77. Erhan Ozalevli, Walter Huang, Paul E. Hasler, David V. Anderson
    VLSI Implementation of a Reconfigurable Mixed-Signal Finite Impulse Response Filter. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:2168-2171 [Conf]
  78. H. Dine, S. Chuang, Phillip E. Allen, Paul E. Hasler
    A rail to rail, slew-boosted pre-charge buffer. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]
  79. Sheng-Yu Peng, Muhammad S. Qureshi, Paul E. Hasler, N. A. Hall, F. L. Degertekin
    High SNR capacitive sensing transducer. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]
  80. Christal Gordon, Amanda Preyer, Karolyn Babalola, Robert J. Butera, Paul E. Hasler
    An artificial synapse for interfacing to biological neurons. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]
  81. Erhan Ozalevli, Muhammad S. Qureshi, Paul E. Hasler
    Low-voltage floating-gate CMOS buffer. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]
  82. Ethan Farquhar, Christal Gordon, Paul E. Hasler
    A field programmable neural array. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]
  83. Erhan Ozalevli, Paul E. Hasler
    A tunable floating gate CMOS resistor for low-power and low-voltage applications. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]

  84. A learning digital computer. [Citation Graph (, )][DBLP]


  85. Rapid Prototyping of Large-scale Analog Circuits With Field Programmable Analog Array. [Citation Graph (, )][DBLP]


  86. Bifurcations in a silicon neuron. [Citation Graph (, )][DBLP]


  87. A 256×256 separable transform CMOS imager. [Citation Graph (, )][DBLP]


  88. A biophysically based dendrite model using programmable floating-gate devices. [Citation Graph (, )][DBLP]


  89. Analog VLSI implementation of support vector machine learning and classification. [Citation Graph (, )][DBLP]


  90. Automated conversion of Simulink designs to analog hardware on an FPAA. [Citation Graph (, )][DBLP]


  91. A floating-gate transistor based continuous-time analog adaptive filter. [Citation Graph (, )][DBLP]


  92. An analog programmable multi-dimensional radial basis function based classifier. [Citation Graph (, )][DBLP]


  93. A programmable analog radial-basis-function based classifier. [Citation Graph (, )][DBLP]


  94. Compressive sensing on a CMOS separable transform image sensor. [Citation Graph (, )][DBLP]


Search in 0.006secs, Finished in 0.459secs
NOTICE1
System may not be available sometimes or not working properly, since it is still in development with continuous upgrades
NOTICE2
The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP
 
Introduction Collection Based Clustering Ranking Paper Based Journals Conferences DB Status Statistics Search
System created by asidirop@csd.auth.gr [http://users.auth.gr/~asidirop/] © 2002
for Data Engineering Laboratory, Department of Informatics, Aristotle University © 2002