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Scott Hauck: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Scott Hauck, Gaetano Borriello
    An evaluation of bipartitioning techniques. [Citation Graph (0, 0)][DBLP]
    ARVLSI, 1995, pp:383-403 [Conf]
  2. Kenneth Eguro, Scott Hauck, Akshay Sharma
    Architecture-adaptive range limit windowing for simulated annealing FPGA placement. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:439-444 [Conf]
  3. Scott Hauck, Stephen Knol
    Data Security for Web-based CAD. [Citation Graph (0, 0)][DBLP]
    DAC, 1998, pp:788-793 [Conf]
  4. Agnieszka C. Miguel, Amanda R. Askew, Alexander Chang, Scott Hauck, Richard E. Ladner, Eve A. Riskin
    Reduced Complexity Wavelet-Based Predictive Coding of Hyperspectral Images for FPGA Implementation. [Citation Graph (0, 0)][DBLP]
    Data Compression Conference, 2004, pp:469-478 [Conf]
  5. Katherine Compton, James Cooley, Stephen Knol, Scott Hauck
    Configuration Relocation and Defragmentation for Reconfigurable Computing. [Citation Graph (0, 0)][DBLP]
    FCCM, 2000, pp:279-280 [Conf]
  6. Prithviraj Banerjee, Nagaraj Shenoy, Alok N. Choudhary, Scott Hauck, C. Bachmann, Malay Haldar, Pramod G. Joisha, Alex K. Jones, Abhay Kanhere, Anshuman Nayak, S. Periyacheri, M. Walkden, David Zaretsky
    A MATLAB Compiler for Distributed, Heterogeneous, Reconfigurable Computing Systems. [Citation Graph (0, 0)][DBLP]
    FCCM, 2000, pp:39-48 [Conf]
  7. Kenneth Eguro, Scott Hauck
    Issues and Approaches to Coarse-Grain Reconfigurable Architecture Development. [Citation Graph (0, 0)][DBLP]
    FCCM, 2003, pp:111-120 [Conf]
  8. Mark L. Chang, Scott Hauck
    Précis: A Design-Time Precision Analysis Tool. [Citation Graph (0, 0)][DBLP]
    FCCM, 2002, pp:229-238 [Conf]
  9. Mark L. Chang, Scott Hauck
    Automated Least-Significant Bit Datapath Optimization for FPGAs. [Citation Graph (0, 0)][DBLP]
    FCCM, 2004, pp:59-67 [Conf]
  10. Thomas W. Fry, Scott Hauck
    Hyperspectral Image Compression on Reconfigurable Platforms. [Citation Graph (0, 0)][DBLP]
    FCCM, 2002, pp:251-260 [Conf]
  11. Michael Haselman, Michael J. Beauchamp, Aaron Wood, Scott Hauck, Keith D. Underwood, K. Scott Hemmert
    A Comparison of Floating Point and Logarithmic Number Systems for FPGAs. [Citation Graph (0, 0)][DBLP]
    FCCM, 2005, pp:181-190 [Conf]
  12. Scott Hauck, Thomas W. Fry, Matthew M. Hosler, Jeffrey P. Kao
    The Chimaera reconfigurable functional unit. [Citation Graph (0, 0)][DBLP]
    FCCM, 1997, pp:87-97 [Conf]
  13. Scott Hauck, Zhiyuan Li, Eric J. Schwabe
    Configuration Compression for the Xilinx XC6200 FPGA. [Citation Graph (0, 0)][DBLP]
    FCCM, 1998, pp:138-146 [Conf]
  14. Scott Hauck, William D. Wilson
    Runlength Compression Techniques for FPGA Configurations. [Citation Graph (0, 0)][DBLP]
    FCCM, 1999, pp:286-0 [Conf]
  15. Mark Holland, Scott Hauck
    Automatic Creation of Domain-Specific Reconfigurable CPLDs for SoC. [Citation Graph (0, 0)][DBLP]
    FCCM, 2005, pp:289-290 [Conf]
  16. Zhiyuan Li, Katherine Compton, Scott Hauck
    Configuration Caching Management Techniques for Reconfigurable Computing. [Citation Graph (0, 0)][DBLP]
    FCCM, 2000, pp:22-38 [Conf]
  17. Shawn Phillips, Scott Hauck
    Automating the Layout of Reconfigurable Subsystems Using Circuit Generators. [Citation Graph (0, 0)][DBLP]
    FCCM, 2005, pp:203-212 [Conf]
  18. Shawn Phillips, Akshay Sharma, Scott Hauck
    Automating the Layout of Reconfigurable Subsystems Via Template Reduction. [Citation Graph (0, 0)][DBLP]
    FCCM, 2004, pp:340-341 [Conf]
  19. Kenneth Eguro, Scott Hauck
    Armada: timing-driven pipeline-aware routing for FPGAs. [Citation Graph (0, 0)][DBLP]
    FPGA, 2006, pp:169-178 [Conf]
  20. Zhiyuan Li, Scott Hauck
    Configuration prefetching techniques for partial reconfigurable coprocessor with relocation and defragmentation. [Citation Graph (0, 0)][DBLP]
    FPGA, 2002, pp:187-195 [Conf]
  21. Katherine Compton, Scott Hauck
    Track placement: orchestrating routing structures to maximize routability. [Citation Graph (0, 0)][DBLP]
    FPGA, 2003, pp:241- [Conf]
  22. Katherine Compton, Scott Hauck
    Flexibility measurement of domain-specific reconfigurable hardware. [Citation Graph (0, 0)][DBLP]
    FPGA, 2004, pp:155-161 [Conf]
  23. Zhiyuan Li, Scott Hauck
    Don't Care Discovery for FPGA Configuration Compression. [Citation Graph (0, 0)][DBLP]
    FPGA, 1999, pp:91-98 [Conf]
  24. Michael J. Beauchamp, Scott Hauck, Keith D. Underwood, K. Scott Hemmert
    Embedded floating-point units in FPGAs. [Citation Graph (0, 0)][DBLP]
    FPGA, 2006, pp:12-20 [Conf]
  25. Mark L. Chang, Scott Hauck
    Least-significant bit optimization techniques for FPGAs. [Citation Graph (0, 0)][DBLP]
    FPGA, 2004, pp:251- [Conf]
  26. Scott Hauck
    Configuration Prefetch for Single Context Reconfigurable Coprocessors. [Citation Graph (0, 0)][DBLP]
    FPGA, 1998, pp:65-74 [Conf]
  27. Scott Hauck, Gaetano Borriello
    Logic Partition Orderings for Multi-FPGA Systems. [Citation Graph (0, 0)][DBLP]
    FPGA, 1995, pp:32-38 [Conf]
  28. Scott Hauck, Gaetano Borriello, Steven M. Burns, Carl Ebeling
    MONTAGNE: An FPL for Synchronous and Asynchronous Circuits. [Citation Graph (0, 0)][DBLP]
    FPL, 1992, pp:44-51 [Conf]
  29. Scott Hauck, Matthew M. Hosler, Thomas W. Fry
    High-Performance Carry Chains for FPGAs. [Citation Graph (0, 0)][DBLP]
    FPGA, 1998, pp:223-233 [Conf]
  30. Mark Holland, Scott Hauck
    Improving performance and robustness of domain-specific CPLDs. [Citation Graph (0, 0)][DBLP]
    FPGA, 2006, pp:50-59 [Conf]
  31. Sinan Kaptanoglu, John East, Tim Garverick, Scott Hauck, Tavana Tavana, Steven Trimberger, Ronnie Vasishta
    Is marriage in the cards for programmable logic, microprocessors and ASICs? [Citation Graph (0, 0)][DBLP]
    FPGA, 2001, pp:111- [Conf]
  32. Chandra Mulpuri, Scott Hauck
    Runtime and quality tradeoffs in FPGA placement and routing. [Citation Graph (0, 0)][DBLP]
    FPGA, 2001, pp:29-36 [Conf]
  33. Akshay Sharma, Katherine Compton, Carl Ebeling, Scott Hauck
    Exploration of pipelined FPGA interconnect structures. [Citation Graph (0, 0)][DBLP]
    FPGA, 2004, pp:13-22 [Conf]
  34. Akshay Sharma, Carl Ebeling, Scott Hauck
    PipeRoute: a pipelining-aware router for FPGAs. [Citation Graph (0, 0)][DBLP]
    FPGA, 2003, pp:68-77 [Conf]
  35. Akshay Sharma, Carl Ebeling, Scott Hauck
    Architecture Adaptive Routability-Driven Placement for FPGAs (abstract only). [Citation Graph (0, 0)][DBLP]
    FPGA, 2005, pp:266- [Conf]
  36. Shawn Phillips, Scott Hauck
    Automatic layout of domain-specific reconfigurable subsystems for system-on-a-chip. [Citation Graph (0, 0)][DBLP]
    FPGA, 2002, pp:165-173 [Conf]
  37. Katherine Compton, Scott Hauck
    Track Placement: Orchestrating Routing Structures to Maximize Routability. [Citation Graph (0, 0)][DBLP]
    FPL, 2003, pp:121-130 [Conf]
  38. Katherine Compton, Akshay Sharma, Shawn Phillips, Scott Hauck
    Flexible Routing Architecture Generation for Domain-Specific Reconfigurable Subsystems. [Citation Graph (0, 0)][DBLP]
    FPL, 2002, pp:59-68 [Conf]
  39. Mark Holland, Scott Hauck
    Automatic Creation of Reconfigurable PALs/PLAs for SoC. [Citation Graph (0, 0)][DBLP]
    FPL, 2004, pp:536-545 [Conf]
  40. Mark Holland, Scott Hauck
    Automatic Creation of Domain-Specific Reconfigurable CPLDs for SoC. [Citation Graph (0, 0)][DBLP]
    FPL, 2005, pp:95-100 [Conf]
  41. Shawn Phillips, Akshay Sharma, Scott Hauck
    Automating the Layout of Reconfigurable Subsystems via Template Reduction. [Citation Graph (0, 0)][DBLP]
    FPL, 2004, pp:857-861 [Conf]
  42. Akshay Sharma, Carl Ebeling, Scott Hauck
    Architecture-Adaptive Routability-Driven Placement for FPGAs. [Citation Graph (0, 0)][DBLP]
    FPL, 2005, pp:427-432 [Conf]
  43. Akshay Sharma, Scott Hauck
    Accelerating FPGA Routing Using Architecture-Adaptive A* Techniques. [Citation Graph (0, 0)][DBLP]
    FPT, 2005, pp:225-232 [Conf]
  44. Morgan Enos, Scott Hauck, Majid Sarrafzadeh
    Replication for logic bipartitioning. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1997, pp:342-349 [Conf]
  45. Scott Hauck, Gaetano Borriello, Carl Ebeling
    Mesh Routing Topologies for Multi-FPGA Systems. [Citation Graph (0, 0)][DBLP]
    ICCD, 1994, pp:170-177 [Conf]
  46. Zhi Alex Ye, Andreas Moshovos, Scott Hauck, Prithviraj Banerjee
    CHIMAERA: a high-performance architecture with a tightly-coupled reconfigurable functional unit. [Citation Graph (0, 0)][DBLP]
    ISCA, 2000, pp:225-235 [Conf]
  47. Scott Hauck
    APHYDS: The Academic Physical Design Skeleton. [Citation Graph (0, 0)][DBLP]
    MSE, 2003, pp:8-9 [Conf]
  48. Mark Holland, James Harris, Scott Hauck
    Harnessing FPGAs for Computer Architecture Education. [Citation Graph (0, 0)][DBLP]
    MSE, 2003, pp:12-13 [Conf]
  49. Katherine Compton, Scott Hauck
    Reconfigurable computing: a survey of systems and software. [Citation Graph (0, 0)][DBLP]
    ACM Comput. Surv., 2002, v:34, n:2, pp:171-210 [Journal]
  50. Mark L. Chang, Scott Hauck
    Précis: A Usercentric Word-Length Optimization Tool. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2005, v:22, n:4, pp:349-361 [Journal]
  51. Scott Hauck, Steven M. Burns, Gaetano Borriello, Carl Ebeling
    An FPGA for Implementing Asynchronous Circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 1994, v:11, n:3, pp:60-69 [Journal]
  52. Katherine Compton, Scott Hauck
    Automatic Design of Area-Efficient Configurable ASIC Cores. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2007, v:56, n:5, pp:662-672 [Journal]
  53. Kenneth Eguro, Scott Hauck
    Resource allocation for coarse-grain FPGA development. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:10, pp:1572-1581 [Journal]
  54. Morgan Enos, Scott Hauck, Majid Sarrafzadeh
    Evaluation and optimization of replication algorithms for logic bipartitioning. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1999, v:18, n:9, pp:1237-1248 [Journal]
  55. Scott Hauck, Gaetano Borriello
    An evaluation of bipartitioning techniques. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1997, v:16, n:8, pp:849-866 [Journal]
  56. Scott Hauck, Gaetano Borriello
    Pin assignment for multi-FPGA systems. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1997, v:16, n:9, pp:956-964 [Journal]
  57. Scott Hauck, Zhiyuan Li, Eric J. Schwabe
    Configuration compression for the Xilinx XC6200 FPGA. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1999, v:18, n:8, pp:1107-1113 [Journal]
  58. Akshay Sharma, Carl Ebeling, Scott Hauck
    PipeRoute: a pipelining-aware router for reconfigurable architectures. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:3, pp:518-532 [Journal]
  59. Thomas W. Fry, Scott Hauck
    SPIHT image compression on FPGAs. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Circuits Syst. Video Techn., 2005, v:15, n:9, pp:1138-1147 [Journal]
  60. Scott Hauck, Thomas W. Fry, Matthew M. Hosler, Jeffrey P. Kao
    The Chimaera reconfigurable functional unit. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2004, v:12, n:2, pp:206-217 [Journal]
  61. Michael J. Beauchamp, Scott Hauck, Keith D. Underwood, K. Scott Hemmert
    Architectural Modifications to Improve Floating-Point Unit Efficiency in FPGAs. [Citation Graph (0, 0)][DBLP]
    FPL, 2006, pp:1-6 [Conf]
  62. Gaetano Borriello, Carl Ebeling, Scott Hauck, Steven M. Burns
    The Triptych FPGA architecture. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1995, v:3, n:4, pp:491-501 [Journal]
  63. Carl Ebeling, Larry McMurchie, Scott Hauck, Steven M. Burns
    Placement and routing tools for the Triptych FPGA. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1995, v:3, n:4, pp:473-482 [Journal]
  64. Scott Hauck, Gaetano Borriello, Carl Ebeling
    Mesh routing topologies for multi-FPGA systems. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1998, v:6, n:3, pp:400-408 [Journal]
  65. Scott Hauck, Matthew M. Hosler, Thomas W. Fry
    High-performance carry chains for FPGA's. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2000, v:8, n:2, pp:138-147 [Journal]
  66. Katherine Compton, Zhiyuan Li, James Cooley, Stephen Knol, Scott Hauck
    Configuration relocation and defragmentation for run-time reconfigurable computing. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2002, v:10, n:3, pp:209-220 [Journal]

  67. Enhancing timing-driven FPGA placement for pipelined netlists. [Citation Graph (, )][DBLP]


  68. Simultaneous Retiming and Placement for Pipelined Netlists. [Citation Graph (, )][DBLP]


  69. Fpga-based data acquisition system for a positron emission tomography (PET) scanner. [Citation Graph (, )][DBLP]


  70. SPR: an architecture-adaptive CGRA mapping tool. [Citation Graph (, )][DBLP]


  71. FPGA-based front-end electronics for positron emission tomography. [Citation Graph (, )][DBLP]


  72. Static versus scheduled interconnect in Coarse-Grained Reconfigurable Arrays. [Citation Graph (, )][DBLP]


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