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Krste Asanovic: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Seongmoo Heo, Ronny Krashinsky, Krste Asanovic
    Activity-Sensitive Flip-Flop and Latch Selection for Reduced Energy. [Citation Graph (0, 0)][DBLP]
    ARVLSI, 2001, pp:59-74 [Conf]
  2. Emmett Witchel, Josh Cates, Krste Asanovic
    Mondrian memory protection. [Citation Graph (0, 0)][DBLP]
    ASPLOS, 2002, pp:304-316 [Conf]
  3. Heidi Pan, Krste Asanovic
    Heads and tails: a variable-length instruction format supporting parallel fetch and decode. [Citation Graph (0, 0)][DBLP]
    CASES, 2001, pp:168-175 [Conf]
  4. Emmett Witchel, Krste Asanovic
    Hardware Works, Software Doesn't: Enforcing Modularity with Mondriaan Memory Protection. [Citation Graph (0, 0)][DBLP]
    HotOS, 2003, pp:139-144 [Conf]
  5. C. Scott Ananian, Krste Asanovic, Bradley C. Kuszmaul, Charles E. Leiserson, Sean Lie
    Unbounded Transactional Memory. [Citation Graph (0, 0)][DBLP]
    HPCA, 2005, pp:316-327 [Conf]
  6. David A. Patterson, Krste Asanovic, Aaron B. Brown, Richard Fromm, Jason Golbus, Benjamin Gribstad, Kimberly Keeton, Christoforos E. Kozyrakis, David Martin, Stylianos Perissakis, Randi Thomas, Noah Treuhaft, Katherine A. Yelick
    Intelligent RAM (IRAM): The Industrial Setting, Applications and Architectures. [Citation Graph (0, 0)][DBLP]
    ICCD, 1997, pp:2-7 [Conf]
  7. Jeff Bilmes, Krste Asanovic, Chee-Whye Chin, James Demmel
    Optimizing Matrix Multiply Using PHiPAC: A Portable, High-Performance, ANSI C Coding Methodology. [Citation Graph (0, 0)][DBLP]
    International Conference on Supercomputing, 1997, pp:340-347 [Conf]
  8. Mark Hampton, Krste Asanovic
    Implementing virtual memory in a vector processor with software restart markers. [Citation Graph (0, 0)][DBLP]
    ICS, 2006, pp:135-144 [Conf]
  9. Seongmoo Heo, Kenneth Barr, Mark Hampton, Krste Asanovic
    Dynamic Fine-Grain Leakage Reduction Using Leakage-Biased Bitlines. [Citation Graph (0, 0)][DBLP]
    ISCA, 2002, pp:137-147 [Conf]
  10. Ronny Krashinsky, Christopher Batten, Mark Hampton, Steve Gerding, Brian Pharris, Jared Casper, Krste Asanovic
    The Vector-Thread Architecture. [Citation Graph (0, 0)][DBLP]
    ISCA, 2004, pp:52-63 [Conf]
  11. Jessica H. Tseng, Krste Asanovic
    Banked Multiported Register Files for High-Frequency Superscalar Microprocessors. [Citation Graph (0, 0)][DBLP]
    ISCA, 2003, pp:62-71 [Conf]
  12. Michael Zhang, Krste Asanovic
    Victim Replication: Maximizing Capacity while Hiding Wire Delay in Tiled Chip Multiprocessors. [Citation Graph (0, 0)][DBLP]
    ISCA, 2005, pp:336-345 [Conf]
  13. Seongmoo Heo, Krste Asanovic
    Power-optimal pipelining in deep submicron technology. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2004, pp:218-223 [Conf]
  14. Seongmoo Heo, Krste Asanovic
    Replacing global wires with an on-chip network: a power analysis. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2005, pp:369-374 [Conf]
  15. Seongmoo Heo, Kenneth Barr, Krste Asanovic
    Reducing power density through activity migration. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2003, pp:217-222 [Conf]
  16. Michael Zhang, Krste Asanovic
    Fine-grain CAM-tag cache resizing using miss tags. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2002, pp:130-135 [Conf]
  17. Krste Asanovic
    A Fast Kohonen Net Implementation for Spert-II. [Citation Graph (0, 0)][DBLP]
    IWANN, 1997, pp:792-800 [Conf]
  18. Christopher Batten, Ronny Krashinsky, Steve Gerding, Krste Asanovic
    Cache Refill/Access Decoupling for Vector Machines. [Citation Graph (0, 0)][DBLP]
    MICRO, 2004, pp:331-342 [Conf]
  19. Luis Villa, Michael Zhang, Krste Asanovic
    Dynamic zero compression for cache energy reduction. [Citation Graph (0, 0)][DBLP]
    MICRO, 2000, pp:214-220 [Conf]
  20. Emmett Witchel, Samuel Larsen, C. Scott Ananian, Krste Asanovic
    Direct addressed caches for reduced power consumption. [Citation Graph (0, 0)][DBLP]
    MICRO, 2001, pp:124-133 [Conf]
  21. Kenneth Barr, Krste Asanovic
    Energy Aware Lossless Data Compression. [Citation Graph (0, 0)][DBLP]
    MobiSys, 2003, pp:- [Conf]
  22. John Wawrzynek, Krste Asanovic, Brian Kingsbury, James Beck, David Johnson, Nelson Morgan
    SPERT-II: A Vector Microprocessor System and its Application to Large Problems in Backpropagation Training. [Citation Graph (0, 0)][DBLP]
    NIPS, 1995, pp:619-625 [Conf]
  23. Jae W. Lee, Krste Asanovic
    METERG: Measurement-Based End-to-End Performance Estimation Technique in QoS-Capable Multiprocessors. [Citation Graph (0, 0)][DBLP]
    IEEE Real Time Technology and Applications Symposium, 2006, pp:135-147 [Conf]
  24. Emmett Witchel, Junghwan Rhee, Krste Asanovic
    Mondrix: memory isolation for linux using mondriaan memory protection. [Citation Graph (0, 0)][DBLP]
    SOSP, 2005, pp:31-44 [Conf]
  25. Christoforos E. Kozyrakis, Stylianos Perissakis, David A. Patterson, Thomas E. Anderson, Krste Asanovic, Neal Cardwell, Richard Fromm, Jason Golbus, Benjamin Gribstad, Kimberly Keeton, Randi Thomas, Noah Treuhaft, Katherine A. Yelick
    Scalable Processors in the Billion-Transistor Era: IRAM. [Citation Graph (0, 0)][DBLP]
    IEEE Computer, 1997, v:30, n:9, pp:75-78 [Journal]
  26. John Wawrzynek, Krste Asanovic, Brian Kingsbury, David Johnson, James Beck, Nelson Morgan
    Spert-II: A Vector Microprocessor System. [Citation Graph (0, 0)][DBLP]
    IEEE Computer, 1996, v:29, n:3, pp:79-86 [Journal]
  27. Krste Asanovic, James Beck, Jerry Feldman, Nelson Morgan, John Wawrzynek
    Designing A Connectionist Network Supercomputer. [Citation Graph (0, 0)][DBLP]
    Int. J. Neural Syst., 1993, v:4, n:4, pp:317-326 [Journal]
  28. C. Scott Ananian, Krste Asanovic, Bradley C. Kuszmaul, Charles E. Leiserson, Sean Lie
    Unbounded Transactional Memory. [Citation Graph (0, 0)][DBLP]
    IEEE Micro, 2006, v:26, n:1, pp:59-69 [Journal]
  29. Ronny Krashinsky, Christopher Batten, Mark Hampton, Steve Gerding, Brian Pharris, Jared Casper, Krste Asanovic
    The Vector-Thread Architecture. [Citation Graph (0, 0)][DBLP]
    IEEE Micro, 2004, v:24, n:6, pp:84-90 [Journal]
  30. Michael Sung, Ronny Krashinsky, Krste Asanovic
    Multithreading decoupled architectures for complexity-effective general purpose computing. [Citation Graph (0, 0)][DBLP]
    SIGARCH Computer Architecture News, 2001, v:29, n:5, pp:56-61 [Journal]
  31. Jessica H. Tseng, Krste Asanovic
    A Speculative Control Scheme for an Energy-Efficient Banked Register Fil. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2005, v:54, n:6, pp:741-751 [Journal]
  32. Kenneth R. Barr, Krste Asanovic
    Energy-aware lossless data compression. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Comput. Syst., 2006, v:24, n:3, pp:250-291 [Journal]
  33. John Wawrzynek, David Patterson, Mark Oskin, Shih-Lien Lu, Christoforos E. Kozyrakis, James C. Hoe, Derek Chiou, Krste Asanovic
    RAMP: Research Accelerator for Multiple Processors. [Citation Graph (0, 0)][DBLP]
    IEEE Micro, 2007, v:27, n:2, pp:46-57 [Journal]
  34. Seongmoo Heo, Ronny Krashinsky, Krste Asanovic
    Activity-Sensitive Flip-Flop and Latch Selection for Reduced Energy. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2007, v:15, n:9, pp:1060-1064 [Journal]

  35. Compiling for vector-thread architectures. [Citation Graph (, )][DBLP]


  36. RAMP gold: an FPGA-based architecture simulator for multiprocessors. [Citation Graph (, )][DBLP]


  37. Building Manycore Processor-to-DRAM Networks with Monolithic Silicon Photonics. [Citation Graph (, )][DBLP]


  38. Continual hashing for efficient fine-grain state inconsistency detection. [Citation Graph (, )][DBLP]


  39. Designing multi-socket systems using silicon photonics. [Citation Graph (, )][DBLP]


  40. Globally-Synchronized Frames for Guaranteed Quality-of-Service in On-Chip Networks. [Citation Graph (, )][DBLP]


  41. Re-architecting DRAM memory systems with monolithically integrated silicon photonics. [Citation Graph (, )][DBLP]


  42. A case for FAME: FPGA architecture model execution. [Citation Graph (, )][DBLP]


  43. Accelerating architectural exploration using canonical instruction segments. [Citation Graph (, )][DBLP]


  44. Branch trace compression for snapshot-based simulation. [Citation Graph (, )][DBLP]


  45. Accelerating Multiprocessor Simulation with a Memory Timestamp Record. [Citation Graph (, )][DBLP]


  46. MEMOCODE 2008 Co-Design Contest. [Citation Graph (, )][DBLP]


  47. Composing parallel software efficiently with lithe. [Citation Graph (, )][DBLP]


  48. Silicon-photonic clos networks for global on-chip communication. [Citation Graph (, )][DBLP]


  49. A view of the parallel computing landscape. [Citation Graph (, )][DBLP]


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