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Kei-Yong Khoo :
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Kei-Yong Khoo , Alan N. Willson Jr. Single-transistor transparent-latch clocking. [Citation Graph (0, 0)][DBLP ] ARVLSI, 1995, pp:331-341 [Conf ] Kei-Yong Khoo , Jason Cong An Efficient Multilayer MCM Router Based on Four-Via Routing. [Citation Graph (0, 0)][DBLP ] DAC, 1993, pp:590-595 [Conf ] Zhan Yu , Kei-Yong Khoo , Alan N. Willson Jr. The use of carry-save representation in joint module selection and retiming. [Citation Graph (0, 0)][DBLP ] DAC, 2000, pp:768-773 [Conf ] Jason Cong , Jie Fang , Kei-Yong Khoo An implicit connection graph maze routing algorithm for ECO routing. [Citation Graph (0, 0)][DBLP ] ICCAD, 1999, pp:163-167 [Conf ] Jason Cong , David Zhigang Pan , Lei He , Cheng-Kok Koh , Kei-Yong Khoo Interconnect design for deep submicron ICs. [Citation Graph (0, 0)][DBLP ] ICCAD, 1997, pp:478-485 [Conf ] Kei-Yong Khoo , Zhan Yu , Alan N. Willson Jr. Bit-level arithmetic optimization for carry-save additions. [Citation Graph (0, 0)][DBLP ] ICCAD, 1999, pp:14-19 [Conf ] Jason Cong , Kei-Yong Khoo A Provable Near-Optimal Algorithm for the Channel Pin Assignment Problem. [Citation Graph (0, 0)][DBLP ] ICCD, 1991, pp:319-322 [Conf ] Kei-Yong Khoo , Alan N. Willson Jr. Cycle-Based Timing Simulations Using Event-Stream. [Citation Graph (0, 0)][DBLP ] ICCD, 1996, pp:460-0 [Conf ] Chao-Liang Chen , Kei-Yong Khoo , Alan N. Willson Jr. An Improved Polynomial-Time Algorithm for Designing Digital Filters with Power-of-Two Coefficients. [Citation Graph (0, 0)][DBLP ] ISCAS, 1995, pp:223-226 [Conf ] Kei-Yong Khoo , Alan N. Willson Jr. Low Power CMOS Clock Buffer. [Citation Graph (0, 0)][DBLP ] ISCAS, 1994, pp:355-358 [Conf ] Kei-Yong Khoo , Alan Kwentus , Alan N. Willson Jr. An efficient 175 MHz programmable FIR digital filter. [Citation Graph (0, 0)][DBLP ] ISCAS, 1993, pp:72-75 [Conf ] Kei-Yong Khoo , Alan N. Willson Jr. Efficient VLSI implementation of N/N integer division. [Citation Graph (0, 0)][DBLP ] ISCAS (1), 2005, pp:672-675 [Conf ] Kei-Yong Khoo , Zhan Yu , Alan N. Willson Jr. Design of optimal hybrid form FIR filter. [Citation Graph (0, 0)][DBLP ] ISCAS (2), 2001, pp:621-624 [Conf ] Kei-Yong Khoo , Zhan Yu , Alan N. Willson Jr. Improved-Booth encoding for low-power multipliers. [Citation Graph (0, 0)][DBLP ] ISCAS (1), 1999, pp:62-65 [Conf ] Kei-Yong Khoo , Chao-Liang Chen , Alan N. Willson Jr. A CMOS pipelined carry-save array using true single-phase single-transistor-latch clocking. [Citation Graph (0, 0)][DBLP ] ISCAS (1), 1999, pp:298-301 [Conf ] Kei-Yong Khoo , Alan N. Willson Jr. Charge recovery on a databus. [Citation Graph (0, 0)][DBLP ] ISLPD, 1995, pp:185-189 [Conf ] Jason Cong , Jie Fang , Kei-Yong Khoo VIA design rule consideration in multi-layer maze routing algorithms. [Citation Graph (0, 0)][DBLP ] ISPD, 1999, pp:214-220 [Conf ] Jason Cong , Jie Fang , Kei-Yong Khoo DUNE: a multi-layer gridless routing system with wire planning. [Citation Graph (0, 0)][DBLP ] ISPD, 2000, pp:12-18 [Conf ] Jason Cong , Jie Fang , Kei-Yong Khoo Via design rule consideration in multilayer maze routing algorithms. [Citation Graph (0, 0)][DBLP ] IEEE Trans. on CAD of Integrated Circuits and Systems, 2000, v:19, n:2, pp:215-223 [Journal ] Jason Cong , Jie Fang , Kei-Yong Khoo DUNE-a multilayer gridless routing system. [Citation Graph (0, 0)][DBLP ] IEEE Trans. on CAD of Integrated Circuits and Systems, 2001, v:20, n:5, pp:633-647 [Journal ] Kei-Yong Khoo , Jason Cong An efficient multilayer MCM router based on four-via routing. [Citation Graph (0, 0)][DBLP ] IEEE Trans. on CAD of Integrated Circuits and Systems, 1995, v:14, n:10, pp:1277-1290 [Journal ] Zhan Yu , Kei-Yong Khoo , Alan N. Willson Jr. Optimal joint module-selection and retiming with carry-save representation. [Citation Graph (0, 0)][DBLP ] IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:7, pp:836-846 [Journal ] Improving Constant-Coefficient Multiplier Verification by Partial Product Identification. [Citation Graph (, )][DBLP ] Search in 0.002secs, Finished in 0.305secs