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Publications of Author

1. George Kornaros, Christoforos E. Kozyrakis, Panagiota Vatsolaki, Manolis Katevenis
   Pipelined Multi-Queue Management in a VLSI ATM Switch Chip with Credit-Based Flow-Control. [Citation Graph (0, 0)][DBLP]
   ARVLSI, 1997, pp:127-144 [Conf]
   
2. George Kornaros, Theofanis Orphanoudakis, Ioannis Papaefstathiou
   GFS: An Efficient Implementation of Fair Scheduling for Mult-Gigabit Packet Networks. [Citation Graph (0, 0)][DBLP]
   ASAP, 2003, pp:389-399 [Conf]
   
3. George Kornaros, Ioannis Papaefstathiou, Aristides Nikologiannis, Nicholaos Zervos
   A fully-programmable memory management system optimizing queue handling at multi-gigabit rates. [Citation Graph (0, 0)][DBLP]
   DAC, 2003, pp:54-59 [Conf]
   
4. Ioannis Papaefstathiou, George Kornaros, Nicholaos Zervos
   Software Processing Performance in Network Processors. [Citation Graph (0, 0)][DBLP]
   DATE, 2004, pp:186-191 [Conf]
   
5. Ioannis Papaefstathiou, Theofanis Orphanoudakis, George Kornaros, Christopher Kachris, Ioannis Mavroidis, Aristides Nikologiannis
   Queue Management in Network Processors. [Citation Graph (0, 0)][DBLP]
   DATE, 2005, pp:112-117 [Conf]
   
6. George Kornaros, Theofanis Orphanoudakis, Nicholaos Zervos
   An Efficient Implementation of Fair Load Balancing over Multi-CPU SOC Architectures. [Citation Graph (0, 0)][DBLP]
   DSD, 2003, pp:197-205 [Conf]
   
7. George Kornaros
   BCB: A Buffered CrossBar Switch Fabric Utilizing Shared Memory. [Citation Graph (0, 0)][DBLP]
   DSD, 2006, pp:180-188 [Conf]
   
8. Ioannis Papaefstathiou, George Kornaros, Nikolaos Chrysos
   A buffered crossbar-based chip interconnection framework supporting quality of service. [Citation Graph (0, 0)][DBLP]
   ACM Great Lakes Symposium on VLSI, 2007, pp:90-95 [Conf]
   
9. George Kornaros, Ioannis Papaefstathiou
   An Innovative Resource Management Scheme for Multi-gigabit Networking Systems. [Citation Graph (0, 0)][DBLP]
   HSNMC, 2003, pp:165-175 [Conf]
   
10. George Kornaros, Theofanis Orphanoudakis, Yannis Papaefstathiou
    Active flow identifiers for scalable, QoS scheduling in 10-Gbps network processors. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2003, pp:97-100 [Conf]
    
11. Ioannis Papaefstathiou, Helen-Catherine Leligou, Theofanis Orphanoudakis, George Kornaros, Nicholaos Zervos, George E. Konstantoulakis
    An innovative scheduling scheme for high-speed network processors. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2003, pp:93-96 [Conf]
    
12. Kyriakos Vlachos, Nikos A. Nikolaou, Theofanis Orphanoudakis, Stylianos Perissakis, Dionisios N. Pnevmatikatos, George Kornaros, J. A. Sanchez, George E. Konstantoulakis
    Processing and Scheduling Components in an Innovative Network Processor Architecture. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2003, pp:195-201 [Conf]
    
13. Ioannis Papaefstathiou, Stylianos Perissakis, Theofanis Orphanoudakis, Nikos A. Nikolaou, George Kornaros, Nicholas Zervos, George E. Konstantoulakis, Dionisios N. Pnevmatikatos, Kyriakos Vlachos
    PRO3: A Hybrid NPU Architecture. [Citation Graph (0, 0)][DBLP]
    IEEE Micro, 2004, v:24, n:5, pp:20-33 [Journal]
    
14. Aristides Nikologiannis, Ioannis Papaefstathiou, George Kornaros, Christopher Kachris
    An FPGA-based queue management system for high speed networking devices. [Citation Graph (0, 0)][DBLP]
    Microprocessors and Microsystems, 2004, v:28, n:5-6, pp:223-236 [Journal]
    
15. Ioannis Papaefstathiou, Theofanis Orphanoudakis, George Kornaros, Christopher Kachris, Ioannis Mavroidis, Aristides Nikologiannis
    Queue Management in Network Processors [Citation Graph (0, 0)][DBLP]
    CoRR, 2007, v:0, n:, pp:- [Journal]
    
16. 
    Architecture and implementation of a Frame Aggregation Unit for optical frame-based switching. [Citation Graph (, )][DBLP]
    
    
17. 
    An Embedded Networking SoC for purely Ethernet MANs/WANs. [Citation Graph (, )][DBLP]