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Manolis Katevenis:
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Publications of Author
- George Kornaros, Christoforos E. Kozyrakis, Panagiota Vatsolaki, Manolis Katevenis
Pipelined Multi-Queue Management in a VLSI ATM Switch Chip with Credit-Based Flow-Control. [Citation Graph (0, 0)][DBLP] ARVLSI, 1997, pp:127-144 [Conf]
- Manolis Katevenis, Nestoras Tzartzanis
Reducing the Branch Penalty by Rearranging Instructions in Double-Width Memory. [Citation Graph (0, 0)][DBLP] ASPLOS, 1991, pp:15-27 [Conf]
- Manolis Katevenis, Panagiota Vatsolaki, Dimitrios N. Serpanos, Evangelos P. Markatos
ATLAS: A Single-Chip ATM Switch for NOWs. [Citation Graph (0, 0)][DBLP] CANPC, 1997, pp:88-101 [Conf]
- Evangelos P. Markatos, Manolis Katevenis, Penny Vatsolaki
The Remote Enqueue Operation on Networks of Workstations. [Citation Graph (0, 0)][DBLP] CANPC, 1998, pp:1-14 [Conf]
- Andrei Vladimirescu, David Weiss, Manolis Katevenis, Zvika Bronstein, Alon Kifir, Karja Danuwidjaja, K. C. Ng, Niraj Jain, Steve Lass
A Vector Hardware Accelerator with Circuit Simulation Emphasis. [Citation Graph (0, 0)][DBLP] DAC, 1987, pp:89-94 [Conf]
- Manolis Katevenis, Dimitrios N. Serpanos, Emmanuel Spyridakis
Credit-Flow-Controlled ATM for MP Interconnection: The ATLAS I Single-Chip ATM Switch. [Citation Graph (0, 0)][DBLP] HPCA, 1998, pp:47-56 [Conf]
- Evangelos P. Markatos, Manolis Katevenis
Telegraphos: High-Performance Networking for Parallel Processing on Workstation Clusters. [Citation Graph (0, 0)][DBLP] HPCA, 1996, pp:144-153 [Conf]
- Evangelos P. Markatos, Manolis Katevenis
User-Level DMA without Operating System Kernel Modification. [Citation Graph (0, 0)][DBLP] HPCA, 1997, pp:322-331 [Conf]
- Manolis Katevenis, Panagiota Vatsolaki, Aristides Efthymiou
Pipelined Memory Shared Buffer for VLSI Switches. [Citation Graph (0, 0)][DBLP] SIGCOMM, 1995, pp:39-48 [Conf]
- Evangelos P. Markatos, Manolis Katevenis, Dionisios N. Pnevmatikatos, Michail Flouris
Secondary Storage Management for Web Proxies. [Citation Graph (0, 0)][DBLP] USENIX Symposium on Internet Technologies and Systems, 1999, pp:- [Conf]
- Manolis Katevenis, Evangelos P. Markatos, Penny Vatsolaki, Chara Xanthaki
The Remote Enqueue Operation on Networks of Workstations. [Citation Graph (0, 0)][DBLP] Informatica (Slovenia), 1999, v:23, n:1, pp:- [Journal]
- Manolis Katevenis, Evangelos P. Markatos, George Kalokerinos, Apostolos Dollas
Telegraphos: A Substrate for High-Performance Computing on Workstation Clusters. [Citation Graph (0, 0)][DBLP] J. Parallel Distrib. Comput., 1997, v:43, n:2, pp:94-108 [Journal]
- Manolis Katevenis, Stefanos Sidiropoulos, Costas Courcoubetis
Weighted Round-Robin Cell Multiplexing in a General-Purpose ATM Switch Chip. [Citation Graph (0, 0)][DBLP] IEEE Journal on Selected Areas in Communications, 1991, v:9, n:8, pp:1265-1279 [Journal]
- Manolis Katevenis, Iakovos Mavroidis, Georgios Sapountzis, Eva Kalyvianaki, Ioannis Mavroidis, Georgios Glykopoulos
Wormhole IP over (connectionless) ATM. [Citation Graph (0, 0)][DBLP] IEEE/ACM Trans. Netw., 2001, v:9, n:5, pp:650-661 [Journal]
- Evangelos P. Markatos, Dionisios N. Pnevmatikatos, Michail Flouris, Manolis Katevenis
Web-conscious storage management for web proxies. [Citation Graph (0, 0)][DBLP] IEEE/ACM Trans. Netw., 2002, v:10, n:6, pp:735-748 [Journal]
- Nikolaos Chrysos, Manolis Katevenis
Scheduling in Non-Blocking Buffered Three-Stage Switching Fabrics. [Citation Graph (0, 0)][DBLP] INFOCOM, 2006, pp:- [Conf]
- Vassilis Papaefstathiou, Dionisios N. Pnevmatikatos, Manolis Marazakis, Giorgos Kalokairinos, Aggelos Ioannou, Michael Papamichael, Stamatis Kavadias, Giorgos Mihelogiannakis, Manolis Katevenis
Prototyping Efficient Interprocessor Communication Mechanisms. [Citation Graph (0, 0)][DBLP] ICSAMOS, 2007, pp:26-33 [Conf]
- George Michelogiannakis, Dionisios N. Pnevmatikatos, Manolis Katevenis
Approaching Ideal NoC Latency with Pre-Configured Routes. [Citation Graph (0, 0)][DBLP] NOCS, 2007, pp:153-162 [Conf]
- Aggelos Ioannou, Manolis Katevenis
Pipelined heap (priority queue) management for advanced scheduling in high-speed networks. [Citation Graph (0, 0)][DBLP] IEEE/ACM Trans. Netw., 2007, v:15, n:2, pp:450-461 [Journal]
On-chip communication and synchronization mechanisms with cache-integrated network interfaces. [Citation Graph (, )][DBLP]
Towards unified mechanisms for inter-processor communication. [Citation Graph (, )][DBLP]
FPGA implementation of a configurable cache/scratchpad memory with virtualized user-level RDMA capability. [Citation Graph (, )][DBLP]
A 128 x 128 x 24Gb/s Crossbar Interconnecting 128 Tiles in a Single Hop and Occupying 6% of Their Area. [Citation Graph (, )][DBLP]
Building an FoC Using Large, Buffered Crossbar Cores. [Citation Graph (, )][DBLP]
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