The SCEAS System
Navigation Menu

Search the dblp DataBase


José Monteiro: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. José Monteiro, John Rinderknecht, Srinivas Devadas, Abhijit Ghosh
    Optimization of combinational and sequential logic circuits for low power using precomputation. [Citation Graph (0, 0)][DBLP]
    ARVLSI, 1995, pp:430-444 [Conf]
  2. Levent Aksoy, Eduardo A. C. da Costa, Paulo F. Flores, José Monteiro
    Optimization of area under a delay constraint in digital filter synthesis using SAT-based integer linear programming. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:669-674 [Conf]
  3. José Monteiro, Srinivas Devadas, Pranav Ashar, Ashutosh Mauskar
    Scheduling Techniques to Enable Power Management. [Citation Graph (0, 0)][DBLP]
    DAC, 1996, pp:349-352 [Conf]
  4. José C. Costa, Srinivas Devadas, José Monteiro
    Observability Analysis of Embedded Software for Coverage-Directed Validation. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2000, pp:27-32 [Conf]
  5. Eduardo A. C. da Costa, Sergio Bampi, José Monteiro
    A New Architecture for Signed Radix-2m Pure Array Multipliers. [Citation Graph (0, 0)][DBLP]
    ICCD, 2002, pp:112-117 [Conf]
  6. José Monteiro, Srinivas Devadas
    Techniques for the power estimation of sequential logic circuits under user-specified input sequences and programs. [Citation Graph (0, 0)][DBLP]
    ISLPD, 1995, pp:33-38 [Conf]
  7. Ricardo Ferreira, A.-M. Trullemans, José C. Costa, José Monteiro
    Probabilistic Bottom-Up RTL Power Estimation. [Citation Graph (0, 0)][DBLP]
    ISQED, 2000, pp:439-0 [Conf]
  8. Eduardo A. C. da Costa, Paulo F. Flores, José Monteiro
    Exploiting general coefficient representation for the optimal sharing of partial products in MCMs. [Citation Graph (0, 0)][DBLP]
    SBCCI, 2006, pp:161-166 [Conf]
  9. Eduardo A. C. da Costa, José Monteiro, Sergio Bampi
    Gray Encoded Arithmetic Operators Applied to FFT and FIR Dedicated Datapaths. [Citation Graph (0, 0)][DBLP]
    VLSI-SOC, 2003, pp:307-0 [Conf]

  10. A new quaternary FPGA based on a voltage-mode multi-valued circuit. [Citation Graph (, )][DBLP]

Search in 0.020secs, Finished in 0.021secs
System may not be available sometimes or not working properly, since it is still in development with continuous upgrades
The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP
System created by [] © 2002
for Data Engineering Laboratory, Department of Informatics, Aristotle University © 2002