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Abhijit Ghosh: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. José Monteiro, John Rinderknecht, Srinivas Devadas, Abhijit Ghosh
    Optimization of combinational and sequential logic circuits for low power using precomputation. [Citation Graph (0, 0)][DBLP]
    ARVLSI, 1995, pp:430-444 [Conf]
  2. Luc Séméria, Abhijit Ghosh
    Methodology for hardware/software co-verification in C/C++ (short paper). [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2000, pp:405-408 [Conf]
  3. Abhijit Ghosh, Srinivas Devadas, Kurt Keutzer, Jacob White
    Estimation of Average Switching Activity in Combinational and Sequential Circuits. [Citation Graph (0, 0)][DBLP]
    DAC, 1992, pp:253-259 [Conf]
  4. Abhijit Ghosh, Srinivas Devadas, A. Richard Newton
    Verification of Interacting Sequential Circuits. [Citation Graph (0, 0)][DBLP]
    DAC, 1990, pp:213-219 [Conf]
  5. Abhijit Ghosh, Srinivas Devadas, A. Richard Newton
    Sequential Test Generation at the Register-Transfer and Logic Levels. [Citation Graph (0, 0)][DBLP]
    DAC, 1990, pp:580-586 [Conf]
  6. Abhijit Ghosh, Joachim Kunkel, Stan Y. Liao
    Hardware Synthesis from C/C++. [Citation Graph (0, 0)][DBLP]
    DATE, 1999, pp:387-389 [Conf]
  7. Abhijit Ghosh, Sandeep K. Lodha, Ranga Vemuri
    Hierarchical Scheduling in High Level Synthesis Using Resource Sharing Across Nested Loops. [Citation Graph (0, 0)][DBLP]
    Great Lakes Symposium on VLSI, 1999, pp:140-143 [Conf]
  8. Mazhar Alidina, José C. Monteiro, Srinivas Devadas, Abhijit Ghosh, Marios C. Papaefthymiou
    Precomputation-based sequential logic optimization for low power. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1994, pp:74-81 [Conf]
  9. Pranav Ashar, Abhijit Ghosh, Srinivas Devadas, A. Richard Newton
    Implicit State Transition Graphs: Applications to Sequential Logic Synthesis and Test. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1990, pp:84-87 [Conf]
  10. Srinivas Devadas, Abhijit Ghosh, Kurt Keutzer
    An observability-based code coverage metric for functional simulation. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1996, pp:418-425 [Conf]
  11. Stan Y. Liao, Srinivas Devadas, Abhijit Ghosh
    Boolean factorization using multiple-valued minimization. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1993, pp:606-611 [Conf]
  12. José C. Monteiro, Srinivas Devadas, Abhijit Ghosh
    Retiming sequential circuits for low power. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1993, pp:398-402 [Conf]
  13. Amelia Shen, Srinivas Devadas, Abhijit Ghosh
    Probabilistic construction and manipulation of free Boolean diagrams. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1993, pp:544-583 [Conf]
  14. Amelia Shen, Abhijit Ghosh, Srinivas Devadas, Kurt Keutzer
    On average power dissipation and random pattern testability of CMOS combinational logic networks. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1992, pp:402-407 [Conf]
  15. Pranav Ashar, Abhijit Ghosh, Srinivas Devadas
    Boolean Satisfiability and Equivalence Checking Using General Binary Decision Diagrams. [Citation Graph (0, 0)][DBLP]
    ICCD, 1991, pp:259-264 [Conf]
  16. Abhijit Ghosh, Ranga Vemuri
    Formal Verification of Synthesized Analog Designs. [Citation Graph (0, 0)][DBLP]
    ICCD, 1999, pp:40-45 [Conf]
  17. Vivek Sinha, Frederic Doucet, Chuck Siska, Rajesh K. Gupta, Stan Y. Liao, Abhijit Ghosh
    YAML: A Tool for Hardware Design Visualization and Capture. [Citation Graph (0, 0)][DBLP]
    ISSS, 2000, pp:9-17 [Conf]
  18. Abhijit Ghosh, Ranga Vemuri
    Formal Verification of Synthesized Mixed Signal Designs Using *BMDs. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2000, pp:84-0 [Conf]
  19. Abhijit Ghosh, Srinivas Devadas, A. Richard Newton
    Test generation and verification for highly sequential circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1991, v:10, n:5, pp:652-667 [Journal]
  20. Abhijit Ghosh, Srinivas Devadas, A. Richard Newton
    Heuristic minimization of Boolean relations using testing techniques. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1992, v:11, n:9, pp:1166-1172 [Journal]
  21. Abhijit Ghosh, Srinivas Devadas, A. Richard Newton
    Sequential test generation and synthesis for testability at the register-transfer and logic levels. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1993, v:12, n:5, pp:579-598 [Journal]
  22. José C. Monteiro, Srinivas Devadas, Abhijit Ghosh
    Sequential logic optimization for low power using input-disabling precomputation architectures. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1998, v:17, n:3, pp:279-284 [Journal]
  23. José C. Monteiro, Srinivas Devadas, Abhijit Ghosh, Kurt Keutzer, Jacob K. White
    Estimation of average switching activity in combinational logic circuits using symbolic simulation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1997, v:16, n:1, pp:121-127 [Journal]
  24. Amelia Shen, Srinivas Devadas, Abhijit Ghosh
    Probabilistic manipulation of Boolean functions using free Boolean diagrams. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1995, v:14, n:1, pp:87-95 [Journal]
  25. Fuchun Joseph Lin, Hong Liu, Abhijit Ghosh
    A Methodology for Feature Interaction Detection in the AIN 0.1 Framework. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Software Eng., 1998, v:24, n:10, pp:797-817 [Journal]
  26. Mazhar Alidina, J. Monteiro, Srinivas Devadas, Abhijit Ghosh, Marios C. Papaefthymiou
    Precomputation-based sequential logic optimization for low power. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1994, v:2, n:4, pp:426-436 [Journal]

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