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Title:
Author:
Wayne Luk: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Andreas Fidjeland, Wayne Luk
    Customising Application-Speci.c Multiprocessor Systems: a Case Study. [Citation Graph (0, 0)][DBLP]
    ASAP, 2005, pp:239-246 [Conf]
  2. Ray C. C. Cheung, Dong-U Lee, Oskar Mencer, Wayne Luk, Peter Y. K. Cheung
    Automating custom-precision function evaluation for embedded processors. [Citation Graph (0, 0)][DBLP]
    CASES, 2005, pp:22-31 [Conf]
  3. Shay Ping Seng, Wayne Luk, Peter Y. K. Cheung
    Flexible instruction processors. [Citation Graph (0, 0)][DBLP]
    CASES, 2000, pp:193-200 [Conf]
  4. Arran Derbyshire, Tobias Becker, Wayne Luk
    Incremental elaboration for run-time reconfigurable hardware designs. [Citation Graph (0, 0)][DBLP]
    CASES, 2006, pp:93-102 [Conf]
  5. Steve McKeever, Wayne Luk
    Towards Provably-Correct Hardware Compilation Tools Based on Pass Separation Techniques. [Citation Graph (0, 0)][DBLP]
    CHARME, 2001, pp:212-227 [Conf]
  6. Oliver Pell, Wayne Luk
    Resolving Quartz Overloading. [Citation Graph (0, 0)][DBLP]
    CHARME, 2005, pp:380-383 [Conf]
  7. Wayne Luk, Teddy Wu
    Towards a declarative framework for hardware-software codesign. [Citation Graph (0, 0)][DBLP]
    CODES, 1994, pp:181-188 [Conf]
  8. Dong-U Lee, Altaf Abdul Gaffar, Oskar Mencer, Wayne Luk
    MiniBit: bit-width optimization via affine arithmetic. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:837-840 [Conf]
  9. George A. Constantinides, Peter Y. K. Cheung, Wayne Luk
    Heuristic datapath allocation for multiple wordlength systems. [Citation Graph (0, 0)][DBLP]
    DATE, 2001, pp:791-797 [Conf]
  10. W. W. S. Chu, R. G. Dimond, S. Perrott, S. P. Seng, W. Luk
    Customisable EPIC Processor: Architecture and Tools. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:236-241 [Conf]
  11. Ray C. C. Cheung, Wayne Luk, Peter Y. K. Cheung
    Reconfigurable Elliptic Curve Cryptosystems on a Chip. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:24-29 [Conf]
  12. Robert G. Dimond, Oskar Mencer, Wayne Luk
    Automating processor customisation: optimised memory access and resource sharing. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:206-211 [Conf]
  13. Suhaib A. Fahmy, Peter Y. K. Cheung, Wayne Luk
    Hardware Acceleration of Hidden Markov Model Decoding for Person Detection. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:8-13 [Conf]
  14. Tero Rissa, Adam Donlin, Wayne Luk
    Evaluation of SystemC Modelling of Reconfigurable Embedded Systems. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:253-258 [Conf]
  15. Tero Rissa, Adam Donlin, Wayne Luk
    Evaluation of SystemC Modelling of Reconfigurable Embedded Systems. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:253-258 [Conf]
  16. Wayne Luk, Sherif Yusuf, Morris Sloman, Geoffrey Brown, Emil C. Lupu, Naranker Dulay
    A Combined Hardware-Software Architecture for Network Flow. [Citation Graph (0, 0)][DBLP]
    ERSA, 2005, pp:149-155 [Conf]
  17. Wim J. C. Melis, Kieron Turkington, Alexander Whitton, Wayne Luk, Peter Y. K. Cheung, Paul Metzgen
    Cell Based Motion Estimators for Reconfigurable Platforms. [Citation Graph (0, 0)][DBLP]
    ERSA, 2005, pp:218-224 [Conf]
  18. Tero Rissa, Wayne Luk, Peter Y. K. Cheung
    Distinguished Paper: Automated Combination of Simulation and Hardware Prototyping. [Citation Graph (0, 0)][DBLP]
    ERSA, 2004, pp:184-193 [Conf]
  19. Per Haglund, Oskar Mencer, Wayne Luk, Benjamin Tai
    PyHDL: Hardware Scripting with Python. [Citation Graph (0, 0)][DBLP]
    Engineering of Reconfigurable Systems and Algorithms, 2003, pp:288-291 [Conf]
  20. Tim Todman, José Gabriel F. Coutinho, Wayne Luk
    Customisable Hardware Compilation. [Citation Graph (0, 0)][DBLP]
    ERSA, 2004, pp:18-28 [Conf]
  21. Chun Hok Ho, Ka Fai Cedric Yiu, Jiaquan Huo, Sven Nordholm, Wayne Luk
    Reconfigurable Acceleration of Robust Frequency-Domain Echo Cancellation. [Citation Graph (0, 0)][DBLP]
    ERSA, 2006, pp:184-190 [Conf]
  22. Altaf Abdul Gaffar, Wayne Luk, Peter Y. K. Cheung, Nabeel Shirazi
    Customising Floating-Point Designs. [Citation Graph (0, 0)][DBLP]
    FCCM, 2002, pp:315-317 [Conf]
  23. Altaf Abdul Gaffar, Oskar Mencer, Wayne Luk, Peter Y. K. Cheung
    Unifying Bit-Width Optimisation for Fixed-Point and Floating-Point Designs. [Citation Graph (0, 0)][DBLP]
    FCCM, 2004, pp:79-88 [Conf]
  24. Jörn Gause, Peter Y. K. Cheung, Wayne Luk
    Reconfigurable Shape-Adaptive Template Matching Architectures. [Citation Graph (0, 0)][DBLP]
    FCCM, 2002, pp:98-0 [Conf]
  25. George A. Constantinides, Peter Y. K. Cheung, Wayne Luk
    Multiple Precision for Resource Minimization. [Citation Graph (0, 0)][DBLP]
    FCCM, 2000, pp:307-308 [Conf]
  26. George A. Constantinides, Peter Y. K. Cheung, Wayne Luk
    Optimum Wordlength Allocation. [Citation Graph (0, 0)][DBLP]
    FCCM, 2002, pp:219-228 [Conf]
  27. José Gabriel F. Coutinho, Jun Jiang, Wayne Luk
    Interleaving Behavioral and Cycle-Accurate Descriptions for Reconfigurable Hardware Compilation. [Citation Graph (0, 0)][DBLP]
    FCCM, 2005, pp:245-254 [Conf]
  28. Paul Baker, Tim Todman, Henry Styles, Wayne Luk
    Reconfigurable Designs for Radiosity. [Citation Graph (0, 0)][DBLP]
    FCCM, 2005, pp:95-104 [Conf]
  29. Arran Derbyshire, Wayne Luk
    Combining Serialization and Reconfiguration for Convolver Designs. [Citation Graph (0, 0)][DBLP]
    FCCM, 2000, pp:344-346 [Conf]
  30. Dan Benyamin, John D. Villasenor, Wayne Luk
    Optimizing FPGA-Based Vector Product Designs. [Citation Graph (0, 0)][DBLP]
    FCCM, 1999, pp:188-0 [Conf]
  31. Simon D. Haynes, Peter Y. K. Cheung, Wayne Luk, John Stone
    SONIC - A Plug-In Architecture for Video Processing. [Citation Graph (0, 0)][DBLP]
    FCCM, 1999, pp:280-281 [Conf]
  32. Dong-U Lee, Wayne Luk, John D. Villasenor, Peter Y. K. Cheung
    A Hardware Gaussian Noise Generator for Channel Code Evaluation. [Citation Graph (0, 0)][DBLP]
    FCCM, 2003, pp:69-0 [Conf]
  33. Dong-U Lee, Wayne Luk, Connie Wang, Christopher Jones, Michael Smith, John D. Villasenor
    A Flexible Hardware Encoder for Low-Density Parity-Check Codes. [Citation Graph (0, 0)][DBLP]
    FCCM, 2004, pp:101-111 [Conf]
  34. T. K. Lee, Sherif Yusuf, Wayne Luk, Morris Sloman, Emil Lupu, Naranker Dulay
    Compiling Policy Descriptions into Reconfigurable Firewall Processors. [Citation Graph (0, 0)][DBLP]
    FCCM, 2003, pp:39-0 [Conf]
  35. Wayne Luk, T. K. Lee, J. Rice, Nabeel Shirazi, Peter Y. K. Cheung
    Reconfigurable Computing for Augmented Reality. [Citation Graph (0, 0)][DBLP]
    FCCM, 1999, pp:136-145 [Conf]
  36. Wayne Luk, Nabeel Shirazi, Peter Y. K. Cheung
    Compilation tools for run-time reconfigurable designs. [Citation Graph (0, 0)][DBLP]
    FCCM, 1997, pp:56-65 [Conf]
  37. Wim J. C. Melis, Peter Y. K. Cheung, Wayne Luk
    Image Registration of Real-Time Video Data Using the SONIC Reconfigurable Computer Platform. [Citation Graph (0, 0)][DBLP]
    FCCM, 2002, pp:3-12 [Conf]
  38. Tim Todman, Wayne Luk
    Real-time Extensions to a C-like Hardware Description Language. [Citation Graph (0, 0)][DBLP]
    FCCM, 2003, pp:302-304 [Conf]
  39. Markus Weinhardt, Wayne Luk
    Evaluating Hardware Compilation Techniques. [Citation Graph (0, 0)][DBLP]
    FCCM, 2000, pp:333-334 [Conf]
  40. Markus Weinhardt, Wayne Luk
    Pipeline Vectorization for Reconfigurable Systems. [Citation Graph (0, 0)][DBLP]
    FCCM, 1999, pp:52-62 [Conf]
  41. Theerayod Wiangtong, Peter Y. K. Cheung, Wayne Luk
    Tabu Search with Intensification Strategy for Functional Partitioning in Hardware-Software Codesign. [Citation Graph (0, 0)][DBLP]
    FCCM, 2002, pp:297-298 [Conf]
  42. N. Pete Sedcole, Peter Y. K. Cheung, George A. Constantinides, Wayne Luk
    A Structured System Methodology for FPGA Based System-on-A-Chip Design. [Citation Graph (0, 0)][DBLP]
    FCCM, 2004, pp:271-272 [Conf]
  43. Henry Styles, Wayne Luk
    Customizing Graphics Applications: Techniques and Programming Interface. [Citation Graph (0, 0)][DBLP]
    FCCM, 2000, pp:77-90 [Conf]
  44. Henry Styles, Wayne Luk
    Accelerating Radiosity Calculations Using Reconfigurable Platforms. [Citation Graph (0, 0)][DBLP]
    FCCM, 2002, pp:279-281 [Conf]
  45. Nabeel Shirazi, Wayne Luk, Peter Y. K. Cheung
    Automating Production of Run-Time Reconfigurable Designs. [Citation Graph (0, 0)][DBLP]
    FCCM, 1998, pp:147-0 [Conf]
  46. David B. Thomas, Wayne Luk
    Efficient Hardware Generation of Random Variates with Arbitrary Distributions. [Citation Graph (0, 0)][DBLP]
    FCCM, 2006, pp:57-66 [Conf]
  47. Oliver Pell, Wayne Luk
    Generating Parametrised Hardware Libraries from Higher-Order Descriptions. [Citation Graph (0, 0)][DBLP]
    FCCM, 2006, pp:297-298 [Conf]
  48. Robert G. Dimond, Oskar Mencer, Wayne Luk
    Combining Instruction Coding and Scheduling to Optimize Energy in System-on-FPGA. [Citation Graph (0, 0)][DBLP]
    FCCM, 2006, pp:175-184 [Conf]
  49. Chun Hok Ho, Philip Heng Wai Leong, Wayne Luk, Steven J. E. Wilton, S. Lopez-Buedo
    Virtual Embedded Blocks: A Methodology for Evaluating Embedded Elements in FPGAs. [Citation Graph (0, 0)][DBLP]
    FCCM, 2006, pp:35-44 [Conf]
  50. Steve McKeever, Wayne Luk, Arran Derbyshire
    Compiling Hardware Descriptions with Relative Placement Information for Parametrised Libraries. [Citation Graph (0, 0)][DBLP]
    FMCAD, 2002, pp:342-359 [Conf]
  51. Florent de Dinechin, Wayne Luk, Steve McKeever
    Towards Adaptable Hierarchical Placement for FPGAs. [Citation Graph (0, 0)][DBLP]
    FPGA, 1999, pp:254- [Conf]
  52. Steven J. E. Wilton, Chun Hok Ho, Philip Heng Wai Leong, Wayne Luk, Bradley R. Quinton
    A synthesizable datapath-oriented embedded FPGA fabric. [Citation Graph (0, 0)][DBLP]
    FPGA, 2007, pp:33-41 [Conf]
  53. Anjit Sekhar Chaudhuri, Peter Y. K. Cheung, Wayne Luk
    A reconfigurable data-localised array for morphological algorithms. [Citation Graph (0, 0)][DBLP]
    FPL, 1997, pp:344-353 [Conf]
  54. George A. Constantinides, Peter Y. K. Cheung, Wayne Luk
    Multiple-Wordlength Resource Binding. [Citation Graph (0, 0)][DBLP]
    FPL, 2000, pp:646-655 [Conf]
  55. George A. Constantinides, Peter Y. K. Cheung, Wayne Luk
    Synthia: Synthesis of Interacting Automata Targeting LUT-based FPGAs. [Citation Graph (0, 0)][DBLP]
    FPL, 1999, pp:323-332 [Conf]
  56. Arran Derbyshire, Wayne Luk
    Combining Serialisation and Reconfiguration for FPGA Designs. [Citation Graph (0, 0)][DBLP]
    FPL, 2000, pp:636-645 [Conf]
  57. Robert G. Dimond, Oskar Mencer, Wayne Luk
    CUSTARD - A Customisable Threaded FPGA Soft Processor and Tools. [Citation Graph (0, 0)][DBLP]
    FPL, 2005, pp:1-6 [Conf]
  58. Suhaib A. Fahmy, Peter Y. K. Cheung, Wayne Luk
    Novel FPGA-Based Implementation of Median and Weighted Median Filters for Image Processing. [Citation Graph (0, 0)][DBLP]
    FPL, 2005, pp:142-147 [Conf]
  59. Altaf Abdul Gaffar, Wayne Luk, Peter Y. K. Cheung, Nabeel Shirazi, James Hwang
    Automating Customisation of Floating-Point Designs. [Citation Graph (0, 0)][DBLP]
    FPL, 2002, pp:523-533 [Conf]
  60. Simon D. Haynes, Peter Y. K. Cheung, Wayne Luk, John Stone
    SONIC - A Plug-In Architecture for Video Processing. [Citation Graph (0, 0)][DBLP]
    FPL, 1999, pp:21-30 [Conf]
  61. Jörn Gause, Peter Y. K. Cheung, Wayne Luk
    Static and Dynamic Reconfigurable Designs for a 2D Shape-Adaptive DCT. [Citation Graph (0, 0)][DBLP]
    FPL, 2000, pp:96-105 [Conf]
  62. Shaori Guo, Wayne Luk
    Compiling Ruby into FPGAs. [Citation Graph (0, 0)][DBLP]
    FPL, 1995, pp:188-197 [Conf]
  63. Per Haglund, Oskar Mencer, Wayne Luk, Benjamin Tai
    Hardware Design with a Scripting Language. [Citation Graph (0, 0)][DBLP]
    FPL, 2003, pp:1040-1043 [Conf]
  64. Jun Jiang, Wayne Luk, Daniel Rueckert
    FPGA-Based Computation of Free-Form Deformations. [Citation Graph (0, 0)][DBLP]
    FPL, 2003, pp:1057-1061 [Conf]
  65. Adrian Lawrence, Andrew Kay, Wayne Luk, Toshio Nomura, Ian Page
    Using Reconfigurable Hardware to Speed up Product Development and Performance. [Citation Graph (0, 0)][DBLP]
    FPL, 1995, pp:111-118 [Conf]
  66. Dong-U Lee, Wayne Luk, John D. Villasenor, Peter Y. K. Cheung
    Non-uniform Segmentation for Hardware Function Evaluation. [Citation Graph (0, 0)][DBLP]
    FPL, 2003, pp:796-807 [Conf]
  67. Dong-U Lee, Oskar Mencer, David J. Pearce, Wayne Luk
    Automating Optimized Table-with-Polynomial Function Evaluation for FPGAs. [Citation Graph (0, 0)][DBLP]
    FPL, 2004, pp:364-373 [Conf]
  68. T. K. Lee, Sherif Yusuf, Wayne Luk, Morris Sloman, Emil Lupu, Naranker Dulay
    Irregular Reconfigurable CAM Structures for Firewall Applications. [Citation Graph (0, 0)][DBLP]
    FPL, 2003, pp:890-899 [Conf]
  69. Wayne Luk, P. Andreou, Arran Derbyshire, F. Dupont-De-Dinechin, J. Rice, Nabeel Shirazi, D. Siganos
    A Reconfigurable Engine for Real-Time Video Processing. [Citation Graph (0, 0)][DBLP]
    FPL, 1998, pp:169-178 [Conf]
  70. Wayne Luk, Arran Derbyshire, Shaori Guo, D. Siganos
    Serial Hardware Libraries for Reconfigurable Designs. [Citation Graph (0, 0)][DBLP]
    FPL, 1999, pp:185-194 [Conf]
  71. Wayne Luk, Shaori Guo, Nabeel Shirazi, N. Zhuang
    A Framework for Developing Parameterised FPGA Libraries. [Citation Graph (0, 0)][DBLP]
    FPL, 1996, pp:24-33 [Conf]
  72. Wayne Luk, Steve McKeever
    Pebble: A Language for Parametrised and Reconfigurable Hardware Design. [Citation Graph (0, 0)][DBLP]
    FPL, 1998, pp:9-18 [Conf]
  73. Wayne Luk, Nabeel Shirazi, Shaori Guo, Peter Y. K. Cheung
    Pipeline morphing and virtual pipelines. [Citation Graph (0, 0)][DBLP]
    FPL, 1997, pp:111-120 [Conf]
  74. Patrick I. Mackinlay, Peter Y. K. Cheung, Wayne Luk, Richard Sandiford
    Riley-2: A flexible platform for codesign and dynamic reconfigurable computing research. [Citation Graph (0, 0)][DBLP]
    FPL, 1997, pp:91-100 [Conf]
  75. Wim J. C. Melis, Peter Y. K. Cheung, Wayne Luk
    Image Registration of Real-Time Broadcast Video Using the UltraSONIC Reconfigurable Computer. [Citation Graph (0, 0)][DBLP]
    FPL, 2002, pp:1148-1151 [Conf]
  76. Oskar Mencer, Nicolas Boullis, Wayne Luk, Henry Styles
    Parameterized Function Evaluation for FPGAs. [Citation Graph (0, 0)][DBLP]
    FPL, 2001, pp:544-554 [Conf]
  77. Mat Newman, Wayne Luk, Ian Page
    Constraint-based Hierarchical Placement of Parallel Programs. [Citation Graph (0, 0)][DBLP]
    FPL, 1994, pp:220-229 [Conf]
  78. N. Pete Sedcole, Peter Y. K. Cheung, George A. Constantinides, Wayne Luk
    A Reconfigurable Platform for Real-Time Embedded Video Image Processing. [Citation Graph (0, 0)][DBLP]
    FPL, 2003, pp:606-615 [Conf]
  79. N. Pete Sedcole, Peter Y. K. Cheung, George A. Constantinides, Wayne Luk
    A Structured Methodology for System-on-an-FPGA Design. [Citation Graph (0, 0)][DBLP]
    FPL, 2004, pp:1047-1051 [Conf]
  80. Shay Ping Seng, Wayne Luk, Peter Y. K. Cheung
    Run-Time Adaptive Flexible Instruction Processors. [Citation Graph (0, 0)][DBLP]
    FPL, 2002, pp:545-555 [Conf]
  81. Tero Rissa, Peter Y. K. Cheung, Wayne Luk
    SoftSONIC: A Customisable Modular Platform for Video Applications. [Citation Graph (0, 0)][DBLP]
    FPL, 2004, pp:54-63 [Conf]
  82. Nabeel Shirazi, Wayne Luk, Dan Benyamin, Peter Y. K. Cheung
    Quantitative Analysis of Run-Time Reconfigurable Database Search. [Citation Graph (0, 0)][DBLP]
    FPL, 1999, pp:253-263 [Conf]
  83. Nabeel Shirazi, Wayne Luk, Peter Y. K. Cheung
    Run-Time Management of Dynamically Recongigurable Designs. [Citation Graph (0, 0)][DBLP]
    FPL, 1998, pp:59-68 [Conf]
  84. Henry Styles, Wayne Luk
    Branch Optimisation Techniques for Hardware Compilation. [Citation Graph (0, 0)][DBLP]
    FPL, 2003, pp:324-333 [Conf]
  85. Henry Styles, Wayne Luk
    Compilation and Management of Phase-Optimized Reconfigurable Systems. [Citation Graph (0, 0)][DBLP]
    FPL, 2005, pp:311-316 [Conf]
  86. David B. Thomas, Wayne Luk
    Implementing Graphics Shaders Using FPGAs. [Citation Graph (0, 0)][DBLP]
    FPL, 2004, pp:1173- [Conf]
  87. Tim Todman, Wayne Luk
    Methods and Tools for High-Resolution Imaging. [Citation Graph (0, 0)][DBLP]
    FPL, 2004, pp:627-636 [Conf]
  88. Chakkapas Visavakul, Peter Y. K. Cheung, Wayne Luk
    A Digit-Serial Structure for Reconfigurable Multipliers. [Citation Graph (0, 0)][DBLP]
    FPL, 2001, pp:565-573 [Conf]
  89. Markus Weinhardt, Wayne Luk
    Task-Parallel Programming of Reconfigurable Systems. [Citation Graph (0, 0)][DBLP]
    FPL, 2001, pp:172-181 [Conf]
  90. Markus Weinhardt, Wayne Luk
    Memory Access Optimization and RAM Inference for Pipeline Vectorization. [Citation Graph (0, 0)][DBLP]
    FPL, 1999, pp:61-70 [Conf]
  91. Theerayod Wiangtong, Peter Y. K. Cheung, Wayne Luk
    A Unified Codesign Run-Time Environment for the UltraSONIC Reconfigurable Computer. [Citation Graph (0, 0)][DBLP]
    FPL, 2003, pp:396-405 [Conf]
  92. Theerayod Wiangtong, Peter Y. K. Cheung, Wayne Luk
    Cluster-Driven Hardware/Software Partitioning and Scheduling Approach for a Reconfigurable Computer System. [Citation Graph (0, 0)][DBLP]
    FPL, 2003, pp:1071-1074 [Conf]
  93. Steven J. E. Wilton, Su-Shin Ang, Wayne Luk
    The Impact of Pipelining on Energy per Operation in Field-Programmable Gate Arrays. [Citation Graph (0, 0)][DBLP]
    FPL, 2004, pp:719-728 [Conf]
  94. Sherif Yusuf, Wayne Luk
    Bitwise Optimised CAM for Network Intrusion Detection Systems. [Citation Graph (0, 0)][DBLP]
    FPL, 2005, pp:444-449 [Conf]
  95. Guanglie Zhang, Philip Heng Wai Leong, Dong-U Lee, John D. Villasenor, Ray C. C. Cheung, Wayne Luk
    Ziggurat-based Hardware Gaussian Random Number Generator. [Citation Graph (0, 0)][DBLP]
    FPL, 2005, pp:275-280 [Conf]
  96. Xue-Jie Zhang, Kam-Wing Ng, Wayne Luk
    A Combined Approach to High-Level Synthesis for Dynamically Reconfigurable Systems. [Citation Graph (0, 0)][DBLP]
    FPL, 2000, pp:361-370 [Conf]
  97. C. T. Chow, L. S. M. Tsui, Philip Heng Wai Leong, Wayne Luk, Steven J. E. Wilton
    Dynamic Voltage Scaling for Commercial FPGAs. [Citation Graph (0, 0)][DBLP]
    FPT, 2005, pp:173-180 [Conf]
  98. Ben Cope, Peter Y. K. Cheung, Wayne Luk, Sarah Witt
    Have GPUs Made FPGAs Redundant in the Field of Video Processing? [Citation Graph (0, 0)][DBLP]
    FPT, 2005, pp:111-118 [Conf]
  99. Andreas Fidjeland, Wayne Luk
    An Overview of High-Level Synthesis of Multiprocessors for Logic Programming. [Citation Graph (0, 0)][DBLP]
    FPT, 2005, pp:333-334 [Conf]
  100. M. P. T. Juvonen, José Gabriel F. Coutinho, J. L. Wang, B. L. Lo, Wayne Luk, Oskar Mencer, G. Z. Yang
    Custom Hardware Architectures for Posture Analysis. [Citation Graph (0, 0)][DBLP]
    FPT, 2005, pp:77-84 [Conf]
  101. David B. Thomas, Wayne Luk
    High Quality Uniform Random Number Generation Through LUT Optimised Linear Recurrences. [Citation Graph (0, 0)][DBLP]
    FPT, 2005, pp:61-68 [Conf]
  102. G. L. Zhang, Philip Heng Wai Leong, Chun Hok Ho, Kuen Hung Tsoi, C. C. C. Cheung, Dong-U Lee, Ray C. C. Cheung, Wayne Luk
    Reconfigurable Acceleration for Monte Carlo Based Financial Simulation. [Citation Graph (0, 0)][DBLP]
    FPT, 2005, pp:215-222 [Conf]
  103. Steve McKeever, Wayne Luk, Arran Derbyshire
    Towards Verifying Parametrised Hardware Libraries with Relative Placement Information. [Citation Graph (0, 0)][DBLP]
    HICSS, 2003, pp:279- [Conf]
  104. Tim Todman, Wayne Luk
    Combining Imperative and Declarative Hardware Descriptions. [Citation Graph (0, 0)][DBLP]
    HICSS, 2003, pp:280- [Conf]
  105. Shaori Guo, Wayne Luk, Penelope Probert
    Developing Parallel Architectures for Range and Image Sensors. [Citation Graph (0, 0)][DBLP]
    ICRA, 1994, pp:2205-2210 [Conf]
  106. Theerayod Wiangtong, Peter Y. K. Cheung, Wayne Luk
    Multitasking in hardware-software codesign for reconfigurable computer. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2003, pp:621-624 [Conf]
  107. Wim J. C. Melis, Peter Y. K. Cheung, Wayne Luk
    Autonomous Memory Block for reconfigurable computing. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2004, pp:581-584 [Conf]
  108. Wayne Luk
    Customising Processors: Design-Time and Run-Time Opportunities. [Citation Graph (0, 0)][DBLP]
    SAMOS, 2004, pp:49-58 [Conf]
  109. Nicolas Telle, Wayne Luk, Ray C. C. Cheung
    Customising Hardware Designs for Elliptic Curve Cryptography. [Citation Graph (0, 0)][DBLP]
    SAMOS, 2004, pp:274-283 [Conf]
  110. Simon D. Haynes, John Stone, Peter Y. K. Cheung, Wayne Luk
    Video Image Processing with the Sonic Architecture. [Citation Graph (0, 0)][DBLP]
    IEEE Computer, 2000, v:33, n:4, pp:50-57 [Journal]
  111. Geoffrey Brown, Wayne Luk, John O'Leary
    Retargeting a Hardware Compiler Using Protokol Converters. [Citation Graph (0, 0)][DBLP]
    Formal Asp. Comput., 1996, v:8, n:2, pp:209-237 [Journal]
  112. Steve McKeever, Wayne Luk
    Provably-correct hardware compilation tools based on pass separation techniques. [Citation Graph (0, 0)][DBLP]
    Formal Asp. Comput., 2006, v:18, n:2, pp:120-142 [Journal]
  113. John O'Leary, Geoffrey Brown, Wayne Luk
    Verified Compilation of Communicating Processes into Clocked Circuits. [Citation Graph (0, 0)][DBLP]
    Formal Asp. Comput., 1997, v:9, n:5-6, pp:537-559 [Journal]
  114. Wayne Luk, Geoffrey Brown
    A Systolic LRU Processor and Its Top-Down Development. [Citation Graph (0, 0)][DBLP]
    Sci. Comput. Program., 1990, v:15, n:2-3, pp:217-233 [Journal]
  115. Dong-U Lee, Wayne Luk, John D. Villasenor, Peter Y. K. Cheung
    A Gaussian Noise Generator for Hardware-Based Simulations. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2004, v:53, n:12, pp:1523-1534 [Journal]
  116. Dong-U Lee, Altaf Abdul Gaffar, Oskar Mencer, Wayne Luk
    Optimizing Hardware Function Evaluation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2005, v:54, n:12, pp:1520-1531 [Journal]
  117. Dong-U Lee, John D. Villasenor, Wayne Luk, Philip Heng Wai Leong
    A Hardware Gaussian Noise Generator Using the Box-Muller Method and Its Error Analysis. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2006, v:55, n:6, pp:659-671 [Journal]
  118. Henry Styles, Wayne Luk
    Exploiting Program Branch Probabilities in Hardware Compilation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2004, v:53, n:11, pp:1408-1419 [Journal]
  119. George A. Constantinides, Peter Y. K. Cheung, Wayne Luk
    Wordlength optimization for linear digital signal processing. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:10, pp:1432-1442 [Journal]
  120. Dong-U Lee, Altaf Abdul Gaffar, Ray C. C. Cheung, Oskar Mencer, Wayne Luk, George A. Constantinides
    Accuracy-Guaranteed Bit-Width Optimization. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:10, pp:1990-2000 [Journal]
  121. Markus Weinhardt, Wayne Luk
    Pipeline vectorization. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2001, v:20, n:2, pp:234-248 [Journal]
  122. Tim Todman, José Gabriel F. Coutinho, Wayne Luk
    Customisable Hardware Compilation. [Citation Graph (0, 0)][DBLP]
    The Journal of Supercomputing, 2005, v:32, n:2, pp:119-137 [Journal]
  123. George A. Constantinides, Peter Y. K. Cheung, Wayne Luk
    Synthesis of saturation arithmetic architectures. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2003, v:8, n:3, pp:334-354 [Journal]
  124. Ray C. C. Cheung, N. J. Telle, Wayne Luk, Peter Y. K. Cheung
    Customizable elliptic curve cryptosystems. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2005, v:13, n:9, pp:1048-1059 [Journal]
  125. George A. Constantinides, Peter Y. K. Cheung, Wayne Luk
    Optimum and heuristic synthesis of multiple word-length architectures. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2005, v:13, n:1, pp:39-57 [Journal]
  126. Dong-U Lee, Wayne Luk, John D. Villasenor, Guanglie Zhang, Philip Heng Wai Leong
    A hardware Gaussian noise generator using the Wallace method. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2005, v:13, n:8, pp:911-920 [Journal]
  127. J. A. Bower, Wayne Luk, Oskar Mencer, Michael J. Flynn, Martin Morf
    Dynamic clock-frequencies for FPGAs. [Citation Graph (0, 0)][DBLP]
    Microprocessors and Microsystems, 2006, v:30, n:6, pp:388-397 [Journal]
  128. Kubilay Atasu, Robert G. Dimond, Oskar Mencer, Wayne Luk, Can C. Özturan, Günhan Dündar
    Optimizing instruction-set extensible processors under data bandwidth constraints. [Citation Graph (0, 0)][DBLP]
    DATE, 2007, pp:588-593 [Conf]
  129. Oliver Pell, Wayne Luk
    Compiling Higher-Order Polymorphic Hardware Descriptions Into Parametrised VHDL Libraries with Flexible Placement Information. [Citation Graph (0, 0)][DBLP]
    FPL, 2006, pp:1-6 [Conf]
  130. Suhaib A. Fahmy, Christos-Savvas Bouganis, Peter Y. K. Cheung, Wayne Luk
    Efficient Realtime FPGA Implementation of the Trace Transform. [Citation Graph (0, 0)][DBLP]
    FPL, 2006, pp:1-6 [Conf]
  131. Terrence S. T. Mak, N. Pete Sedcole, Peter Y. K. Cheung, Wayne Luk
    On-FPGA Communication Architectures and Design Factors. [Citation Graph (0, 0)][DBLP]
    FPL, 2006, pp:1-8 [Conf]
  132. David B. Thomas, Wayne Luk
    Non-Uniform Random Number Generation Through Piecewise Linear Approximations. [Citation Graph (0, 0)][DBLP]
    FPL, 2006, pp:1-6 [Conf]
  133. Andreas Fidjeland, Wayne Luk
    Archlog: High-Level Synthesis of Reconfigurable Multiprocessors for Logic Programming. [Citation Graph (0, 0)][DBLP]
    FPL, 2006, pp:1-6 [Conf]
  134. N. Pete Sedcole, Peter Y. K. Cheung, George A. Constantinides, Wayne Luk
    On-Chip Communication in Run-Time Assembled Reconfigurable Systems. [Citation Graph (0, 0)][DBLP]
    ICSAMOS, 2006, pp:168-176 [Conf]
  135. Sherif Yusuf, Wayne Luk, M. K. N. Szeto, W. Osborne
    UNITE: Uniform Hardware-Based Network Intrusion deTection Engine. [Citation Graph (0, 0)][DBLP]
    ARC, 2006, pp:389-400 [Conf]
  136. David B. Thomas, Wayne Luk, Michael Stumpf
    Reconfigurable Hardware Acceleration of Canonical Graph Labelling. [Citation Graph (0, 0)][DBLP]
    ARC, 2007, pp:302-313 [Conf]
  137. Su-Shin Ang, George A. Constantinides, Peter Y. K. Cheung, Wayne Luk
    A Flexible Multi-port Caching Scheme for Reconfigurable Platforms. [Citation Graph (0, 0)][DBLP]
    ARC, 2006, pp:205-216 [Conf]
  138. Terrence S. T. Mak, N. Pete Sedcole, Peter Y. K. Cheung, Wayne Luk, K. P. Lam
    A Hybrid Analog-Digital Routing Network for NoC Dynamic Routing. [Citation Graph (0, 0)][DBLP]
    NOCS, 2007, pp:173-182 [Conf]
  139. Tero Rissa, Adam Donlin, Wayne Luk
    Evaluation of SystemC Modelling of Reconfigurable Embedded Systems [Citation Graph (0, 0)][DBLP]
    CoRR, 2007, v:0, n:, pp:- [Journal]
  140. David B. Thomas, Wayne Luk, Philip Heng Wai Leong, John D. Villasenor
    Gaussian random number generators. [Citation Graph (0, 0)][DBLP]
    ACM Comput. Surv., 2007, v:39, n:4, pp:- [Journal]
  141. N. Pete Sedcole, Peter Y. K. Cheung, George A. Constantinides, Wayne Luk
    Run-Time Integration of Reconfigurable Video Processing Systems. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2007, v:15, n:9, pp:1003-1016 [Journal]
  142. Ray C. C. Cheung, Dong-U Lee, Wayne Luk, John D. Villasenor
    Hardware Generation of Arbitrary Random Number Distributions From Uniform Distributions Via the Inversion Method. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2007, v:15, n:8, pp:952-962 [Journal]
  143. José Gabriel F. Coutinho, M. P. T. Juvonen, J. L. Wang, B. L. Lo, Wayne Luk, Oskar Mencer, G. Z. Yang
    Designing a Posture Analysis System with Hardware Implementation. [Citation Graph (0, 0)][DBLP]
    VLSI Signal Processing, 2007, v:47, n:1, pp:33-45 [Journal]
  144. David B. Thomas, Wayne Luk
    High Quality Uniform Random Number Generation Using LUT Optimised State-transition Matrices. [Citation Graph (0, 0)][DBLP]
    VLSI Signal Processing, 2007, v:47, n:1, pp:77-92 [Journal]

  145. Automatic Generation and Optimisation of Reconfigurable Financial Monte-Carlo Simulations. [Citation Graph (, )][DBLP]


  146. Bridging the Gap between FPGAs and Multi-Processor Architectures: A Video Processing Perspective. [Citation Graph (, )][DBLP]


  147. Resource efficient generators for the floating-point uniform and exponential distributions. [Citation Graph (, )][DBLP]


  148. Reconfigurable acceleration of microphone array algorithms for speech enhancement. [Citation Graph (, )][DBLP]


  149. Fast custom instruction identification by convex subgraph enumeration. [Citation Graph (, )][DBLP]


  150. Accelerating a Virtual Ecology Model with FPGAs. [Citation Graph (, )][DBLP]


  151. NeMo: A Platform for Neural Modelling of Spiking Neurons Using GPUs. [Citation Graph (, )][DBLP]


  152. A DP-network for optimal dynamic routing in network-on-chip. [Citation Graph (, )][DBLP]


  153. Using Reconfigurable Logic to Optimise GPU Memory Accesses. [Citation Graph (, )][DBLP]


  154. Partition-based exploration for reconfigurable JPEG designs. [Citation Graph (, )][DBLP]


  155. Design optimizations to improve placeability of partial reconfiguration modules. [Citation Graph (, )][DBLP]


  156. Exploration of hardware sharing for image encoders. [Citation Graph (, )][DBLP]


  157. Combining optimizations in automated low power design. [Citation Graph (, )][DBLP]


  158. Harnessing Human Computation Cycles for the FPGA Placement Problem. [Citation Graph (, )][DBLP]


  159. Credit Risk Modelling using Hardware Accelerated Monte-Carlo Simulation. [Citation Graph (, )][DBLP]


  160. A Hybrid Memory Sub-system for Video Coding Applications. [Citation Graph (, )][DBLP]


  161. Sampling from the Multivariate Gaussian Distribution using Reconfigurable Hardware. [Citation Graph (, )][DBLP]


  162. Optimizing Logarithmic Arithmetic on FPGAs. [Citation Graph (, )][DBLP]


  163. Enhancing Relocatability of Partial Bitstreams for Run-Time Reconfiguration. [Citation Graph (, )][DBLP]


  164. Power-Aware and Branch-Aware Word-Length Optimization. [Citation Graph (, )][DBLP]


  165. Accelerating Quadrature Methods for Option Valuation. [Citation Graph (, )][DBLP]


  166. Benchmarking Reconfigurable Architectures in the Mobile Domain. [Citation Graph (, )][DBLP]


  167. FPGA Accelerated Simulation of Biologically Plausible Spiking Neural Networks. [Citation Graph (, )][DBLP]


  168. FPGA-optimised high-quality uniform random number generators. [Citation Graph (, )][DBLP]


  169. High-throughput interconnect wave-pipelining for global communication in FPGAs. [Citation Graph (, )][DBLP]


  170. A comparison of CPUs, GPUs, FPGAs, and massively parallel processor arrays for random number generation. [Citation Graph (, )][DBLP]


  171. Axel: a heterogeneous cluster with FPGAs and GPUs. [Citation Graph (, )][DBLP]


  172. Domain-Specific Hybrid FPGA: Architecture and Floating Point Applications. [Citation Graph (, )][DBLP]


  173. Automatic Accuracy-Guaranteed Bit-Width Optimization for Fixed and Floating-Point Systems. [Citation Graph (, )][DBLP]


  174. Sampling from the exponential distribution using independent Bernoulli variates. [Citation Graph (, )][DBLP]


  175. Mapping and scheduling with task clustering for heterogeneous computing systems. [Citation Graph (, )][DBLP]


  176. A hardware compilation flow for instance-specific VLIW cores. [Citation Graph (, )][DBLP]


  177. Rapid estimation of power consumption for hybrid FPGAs. [Citation Graph (, )][DBLP]


  178. An analytical model describing the relationships between logic architecture and FPGA density. [Citation Graph (, )][DBLP]


  179. Towards benchmarking energy efficiency of reconfigurable architectures. [Citation Graph (, )][DBLP]


  180. Exploring reconfigurable architectures for explicit finite difference option pricing models. [Citation Graph (, )][DBLP]


  181. Modeling post-techmapping and post-clustering FPGA circuit depth. [Citation Graph (, )][DBLP]


  182. Optimising designs by combining model-based and pattern-based transformations. [Citation Graph (, )][DBLP]


  183. Smart Enumeration: A Systematic Approach to Exhaustive Search. [Citation Graph (, )][DBLP]


  184. Reconfigurable design with clock gating. [Citation Graph (, )][DBLP]


  185. Systematic design space exploration for customisable multi-processor architectures. [Citation Graph (, )][DBLP]


  186. Interconnection lengths and delays estimation for communication links in FPGAs. [Citation Graph (, )][DBLP]


  187. Global interconnections in FPGAs: modeling and performance analysis. [Citation Graph (, )][DBLP]


  188. Design Validation by Symbolic Simulation and Equivalence Checking: A Case Study in Memory Optimization for Image Manipulation. [Citation Graph (, )][DBLP]


  189. Parametric Design for Reconfigurable Software-Defined Radio. [Citation Graph (, )][DBLP]


  190. Exploring Reconfigurable Architectures for Binomial-Tree Pricing Models. [Citation Graph (, )][DBLP]


  191. An FPGA run-time parameterisable Log-Normal Random Number Generator. [Citation Graph (, )][DBLP]


  192. Parametric Encryption Hardware Design. [Citation Graph (, )][DBLP]


  193. Implementation of Wave-Pipelined Interconnects in FPGAs. [Citation Graph (, )][DBLP]


  194. Domain Specific Transformations for Hardware Ray Tracing. [Citation Graph (, )][DBLP]


  195. A Customisable Multiprocessor for Application-Optimised Inductive Logic Programming. [Citation Graph (, )][DBLP]


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