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Myung Hoon Sunwoo: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Hyunman Chang, Soohwan Ong, Myung Hoon Sunwoo
    A Linear Array Parallel Image Processor: SliM-II. [Citation Graph (0, 0)][DBLP]
    ASAP, 1997, pp:34-41 [Conf]
  2. Kyung Lan Heo, Sung M. Cho, Jung Hoo Lee, Myung Hoon Sunwoo
    Application-Specific DSP Architecture For Fast Fourier Transform. [Citation Graph (0, 0)][DBLP]
    ASAP, 2003, pp:369-377 [Conf]
  3. Myung Hoon Sunwoo, Soohwan Ong, Byungdug Ahn, Kyungwoo Lee
    Design and Implementation of a Parallel Image Processor Chip for a SIMD Array Processor. [Citation Graph (0, 0)][DBLP]
    ASAP, 1995, pp:66-75 [Conf]
  4. Se Young Eun, Myung Hoon Sunwoo
    An Effcient 2-D Convolver Chip for Real Time Image Processing. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 1998, pp:329-330 [Conf]
  5. Sung Dae Kim, Jeong Hoo Lee, Chung Jin Hyun, Myung Hoon Sunwoo
    ASIP approach for implementation of H.264/AVC. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2006, pp:758-764 [Conf]
  6. Sung Hyun Yoon, Myung Hoon Sunwoo
    An Efficient Variable-Length Tap FIR Filter Chip. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 1998, pp:157-161 [Conf]
  7. Hyunman Chang, Changhee Lee, Myung Hoon Sunwoo
    SliM-II: A Linear Array SIMD Processor for Real-time Image Processing. [Citation Graph (0, 0)][DBLP]
    ICPADS, 1997, pp:132-137 [Conf]
  8. Myung Hoon Sunwoo, J. K. Aggarwal
    Flexibly Coupled Multiprocessors for Image Processing. [Citation Graph (0, 0)][DBLP]
    ICPP (1), 1988, pp:452-461 [Conf]
  9. Hyun M. Chang, Myung Hoon Sunwoo, Tai-Hoon Cho
    Implementation of a SliM Array Processor. [Citation Graph (0, 0)][DBLP]
    IPPS, 1996, pp:771-775 [Conf]
  10. Jaehyun Baek, Ju Hyung Hong, Myung Hoon Sunwoo
    Novel digital signal processing unit for Ethernet receiver. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2005, pp:4477-4480 [Conf]
  11. Jaehyun Baek, Byung S. Son, Byung G. Jo, Myung Hoon Sunwoo, Seung Keun Oh
    A continuous flow mixed-radix FFT architecture with an in-place algorithm. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2003, pp:133-136 [Conf]
  12. Jeong Hoo Lee, Jong Ha Moon, Kyung Lan Heo, Myung Hoon Sunwoo, Seung Keun Oh, In Ho Kim
    Implementation of application-specific DSP for OFDM systems. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2004, pp:665-658 [Conf]
  13. Jung Hoo Lee, Weon Heum Park, Ju Hyung Hong, Myung Hoon Sunwoo, Kyung Ho Kim
    A high-speed blind DFE equalizer using an error feedback filter for QAM modems. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2003, pp:464-467 [Conf]
  14. Suk Hyun Yoon, Jong Ha Moon, Myung Hoon Sunwoo
    Efficient DSP architecture for high-quality audio algorithms. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2005, pp:2947-2950 [Conf]
  15. Byung G. Jo, J. Y. Kang, Myung Hoon Sunwoo
    A low power and area efficient FIR filter chip for PRML read channels. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:606-609 [Conf]
  16. Hyunman Chang, Myung Hoon Sunwoo
    A low complexity Reed-Solomon architecture using the Euclid's algorithm. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 1999, pp:513-516 [Conf]
  17. Soohwan Ong, Hyunjune Yoo, Myung Hoon Sunwoo
    A MDSP (multimedia DSP) chip for portable multimedia applications. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 1999, pp:283-286 [Conf]
  18. Sung Dae Kim, Sug Hyun Jeong, Myung Hoon Sunwoo, Kyung Ho Kim
    Novel bit manipulation unit for communication digital signal processors. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2004, pp:385-388 [Conf]
  19. Byung S. Son, Byung G. Jo, Myung Hoon Sunwoo, Yong Serk Kim
    A high-speed FFT processor for OFDM systems. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2002, pp:281-284 [Conf]
  20. Jung Hoo Lee, Jae Sung Lee, Myung Hoon Sunwoo, Kyung Ho Kim
    Design of new DSP instructions and their hardware architecture for the Viterbi decoding algorithm. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2002, pp:561-564 [Conf]
  21. Jae H. Baek, J. Y. Kang, Myung Hoon Sunwoo
    Design of a high-speed Reed-Solomon decoder. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2002, pp:793-796 [Conf]
  22. Soohwan Ong, Myung Hoon Sunwoo
    Implementation of a Sliding Memory Plane Image Processor. [Citation Graph (0, 0)][DBLP]
    J. Parallel Distrib. Comput., 1998, v:55, n:2, pp:236-248 [Journal]
  23. Myung Hoon Sunwoo, J. K. Aggarwal
    Flexibly Coupled Multiprocessors for Image Processing. [Citation Graph (0, 0)][DBLP]
    J. Parallel Distrib. Comput., 1990, v:10, n:2, pp:115-129 [Journal]
  24. Myung Hoon Sunwoo, J. K. Aggarwal
    A Sliding Memory Plane Array Processor. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Parallel Distrib. Syst., 1993, v:4, n:6, pp:601-612 [Journal]
  25. Jae H. Baek, Myung Hoon Sunwoo
    New degree computationless modified euclid algorithm and architecture for Reed-Solomon decoder. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2006, v:14, n:8, pp:915-920 [Journal]
  26. Sung Dae Kim, Myung Hoon Sunwoo
    Low Power ASIP Architecture Optimization based on Target Application Profiling. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:3764-3767 [Conf]
  27. Jaehyun Baek, Myung Hoon Sunwoo
    Simplified Degree Computationless Modified Euclid's Algorithm and its Architecture. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:905-908 [Conf]
  28. Han Jae Hee, Myung Hoon Sunwoo, Jong Ha Moon
    Novel Non-linear Inverse Quantization Algorithm and its Architecture for Digital Audio Codecs. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:357-360 [Conf]
  29. Jaehyun Baek, Myung Hoon Sunwoo
    Enhanced degree computationless modified Euclid's algorithm for Reed-Solomon decoder. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]

  30. Novel residual prediction scheme for hybrid video coding. [Citation Graph (, )][DBLP]


  31. Novel fractional pixel motion estimation algorithm using motion prediction and fast search pattern. [Citation Graph (, )][DBLP]


  32. Efficient frame selection schemes for multi-reference and variable block size Motion Estimation. [Citation Graph (, )][DBLP]


  33. Novel instructions and their hardware architecture for video signal processing. [Citation Graph (, )][DBLP]


  34. Efficient coarse frequency synchronizer using serial correlator for DVB-S2. [Citation Graph (, )][DBLP]


  35. Enhanced Degree Computationless Modified Euclid's Algorithm. [Citation Graph (, )][DBLP]


  36. VSIP : Implementation of Video Specific Instruction-set Processor. [Citation Graph (, )][DBLP]


  37. Data-aided algorithm based frequency synchronizer for DVB-S2. [Citation Graph (, )][DBLP]


  38. Simplified sum-product algorithm using piecewise linear function approximation for low complexity LDPC decoding. [Citation Graph (, )][DBLP]


  39. AN ASIP Approach for H.264/AVC Implementation Having Novel Coprocessors. [Citation Graph (, )][DBLP]


  40. An Efficient Data-Aided Initial Frequency Synchronizer for DVB-S2. [Citation Graph (, )][DBLP]


  41. Fast multiple reference frame selection methods for H.264/AVC. [Citation Graph (, )][DBLP]


  42. New simplified sum-product algorithm for low complexity LDPC decoding. [Citation Graph (, )][DBLP]


  43. VSIP : Video Specific Instruction Set Processor for H.264/AVC. [Citation Graph (, )][DBLP]


  44. Efficient Memory Reuse and Sub-Pixel Interpolation Algorithms for ME/MC of H.264/AVC. [Citation Graph (, )][DBLP]


  45. Multi-level modulation soft-decision demapper for DVB-S2. [Citation Graph (, )][DBLP]


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