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François Charot: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. François Charot, Madeleine Nyamsi, Patrice Quinton, Charles Wagner
    Modeling and Scheduling Parallel Data Flow Systems using Structured Systems of Recurrence Equations. [Citation Graph (0, 0)][DBLP]
    ASAP, 2004, pp:6-16 [Conf]
  2. Ronan Barzic, Christian Bouville, François Charot, Gwendal Le Fol, Pascal Lemonnier, Charles Wagner
    MOVIE: A Building Block for the Design of Real Time Simulator of Moving Pictures Compression Algorithms. [Citation Graph (0, 0)][DBLP]
    ASAP, 1995, pp:193-203 [Conf]
  3. Daniel Menard, Daniel Chillet, François Charot, Olivier Sentieys
    Automatic floating-point to fixed-point conversion for DSP code generation. [Citation Graph (0, 0)][DBLP]
    CASES, 2002, pp:270-276 [Conf]
  4. François Charot, Vincent Messé
    A flexible code generation framework for the design of application specific programmable processors. [Citation Graph (0, 0)][DBLP]
    CODES, 1999, pp:27-31 [Conf]
  5. Reid B. Porter, Jan R. Frigo, Maya Gokhale, Christophe Wolinski, François Charot, Charles Wagner
    A Run-Time Re-configurable Parametric Architecture for Local Neighborhood Image Processing. [Citation Graph (0, 0)][DBLP]
    DSD, 2006, pp:107-115 [Conf]
  6. Reid B. Porter, Jan R. Frigo, Maya Gokhale, Christophe Wolinski, François Charot, Charles Wagner
    A Programmable, Maximal Throughput Architecture for Neighborhood Image Processing. [Citation Graph (0, 0)][DBLP]
    FCCM, 2006, pp:279-280 [Conf]
  7. François Charot, Eslam Yahya, Charles Wagner
    Efficient Modular-Pipelined AES Implemenation in Counter Mode on ALTERA FPGA. [Citation Graph (0, 0)][DBLP]
    FPL, 2003, pp:282-291 [Conf]
  8. Viorela Ila, Rafael García, François Charot, Joan Batlle
    FPGA Implementation of a Vision-Based Motion Estimation Algorithm for an Underwater Robot. [Citation Graph (0, 0)][DBLP]
    FPL, 2004, pp:1152-1154 [Conf]
  9. François Charot, Patrice Frison, Eric Gautrin, Dominique Lavenier, Patrice Quinton, Charles Wagner
    From Equations to Hardware: Towards Systematic Mapping of Algorithms onto Parallel Architectures. [Citation Graph (0, 0)][DBLP]
    ICPIA, 1992, pp:1-15 [Conf]
  10. Viorela Ila, Rafael García, François Charot
    Proposal of a Parallel Architecture for a Motion Detection Algorithm. [Citation Graph (0, 0)][DBLP]
    ICPR (1), 2004, pp:797-800 [Conf]
  11. François Bodin, François Charot
    Loop optimization for horizontal microcoded machines. [Citation Graph (0, 0)][DBLP]
    ICS, 1990, pp:164-176 [Conf]
  12. François Bodin, François Charot, Charles Wagner
    Overview of a high-performance programmable pipeline structure. [Citation Graph (0, 0)][DBLP]
    ICS, 1989, pp:398-409 [Conf]
  13. François Charot, Madeleine Nyamsi, Patrice Quinton, Charles Wagner
    Architecture Exploration for 3G Telephony Applications Using a Hardware-Software Prototyping Platform. [Citation Graph (0, 0)][DBLP]
    SAMOS, 2004, pp:244-253 [Conf]
  14. Patrice Frison, François Charot, Eric Gautrin, Dominique Lavenier, Patrice Quinton, Frédéric Raimbault, Charles Wagner
    From Equations to Hardware. Towards the Systematic Mapping of Algorithms onto Parallel Architectures. [Citation Graph (0, 0)][DBLP]
    IJPRAI, 1994, v:8, n:2, pp:417-438 [Journal]
  15. Étienne Mémin, Fabrice Heitz, François Charot
    Efficient Parallel Nonlinear Multigrid Algorithms for Low-Level Vision Applications. [Citation Graph (0, 0)][DBLP]
    J. Parallel Distrib. Comput., 1995, v:29, n:1, pp:96-103 [Journal]
  16. François Charot, Claude Labit, Pascal Lemonnier
    Architectural Study of a Block-Recursive Motion Estimation Algorithm. [Citation Graph (0, 0)][DBLP]
    Real-Time Imaging, 1997, v:3, n:2, pp:111-128 [Journal]

  17. Constraint-Driven Instructions Selection and Application Scheduling in the DURASE system. [Citation Graph (, )][DBLP]


  18. A generic architecture of CCSDS Low Density Parity Check decoder for near-earth applications. [Citation Graph (, )][DBLP]


  19. A Parallel and Modular Architecture for 802.16e LDPC Codes. [Citation Graph (, )][DBLP]


  20. Architecture-Driven Synthesis of Reconfigurable Cells. [Citation Graph (, )][DBLP]


  21. A New High Performance Multi Gigabit String Matching Engine. [Citation Graph (, )][DBLP]


  22. How Constrains Programming Can Help You in the Generation of Optimized Application Specific Reconfigurable Processor Extensions. [Citation Graph (, )][DBLP]


  23. A New Powerful Scalable Generic Multi-Standard LDPC Decoder Architecture. [Citation Graph (, )][DBLP]


  24. Energy efficient sensor node implementations. [Citation Graph (, )][DBLP]


  25. Constraint-Driven Identification of Application Specific Instructions in the DURASE System. [Citation Graph (, )][DBLP]


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