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Maurizio Palesi: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi, Davide Patti
    Exploring Design Space of VLIW Architectures. [Citation Graph (0, 0)][DBLP]
    ASAP, 2005, pp:86-91 [Conf]
  2. Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi
    A Framework for Design Space Exploration of Parameterized VLSI Systems. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2002, pp:245-250 [Conf]
  3. Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi, Davide Patti
    A system-level framework for evaluating area/performance/power trade-offs of VLIW-based embedded systems. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2005, pp:940-943 [Conf]
  4. Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi
    Parameterised system design based on genetic algorithms. [Citation Graph (0, 0)][DBLP]
    CODES, 2001, pp:177-182 [Conf]
  5. Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi
    Multi-objective mapping for mesh-based NoC architectures. [Citation Graph (0, 0)][DBLP]
    CODES+ISSS, 2004, pp:182-187 [Conf]
  6. Maurizio Palesi, Tony Givargis
    Multi-objective design space exploration using genetic algorithms. [Citation Graph (0, 0)][DBLP]
    CODES, 2002, pp:67-72 [Conf]
  7. Maurizio Palesi, Rickard Holsmark, Shashi Kumar, Vincenzo Catania
    A methodology for design of application specific deadlock-free routing algorithms for NoC systems. [Citation Graph (0, 0)][DBLP]
    CODES+ISSS, 2006, pp:142-147 [Conf]
  8. Alessandro G. Di Nuovo, Maurizio Palesi, Davide Patti, Giuseppe Ascia, Vincenzo Catania
    Fuzzy decision making in embedded system design. [Citation Graph (0, 0)][DBLP]
    CODES+ISSS, 2006, pp:223-228 [Conf]
  9. Rickard Holsmark, Maurizio Palesi, Shashi Kumar
    Deadlock Free Routing Algorithms for Mesh Topology NoC Systems with Regions. [Citation Graph (0, 0)][DBLP]
    DSD, 2006, pp:696-703 [Conf]
  10. Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi, Davide Patti
    Multi-objective Optimization of a Parameterized VLIW Architecture. [Citation Graph (0, 0)][DBLP]
    Evolvable Hardware, 2004, pp:191-198 [Conf]
  11. Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi, Davide Patti
    EPIC-Explorer: A Parameterized VLIW-based Platform Framework for Design Space Exploration. [Citation Graph (0, 0)][DBLP]
    ESTImedia, 2003, pp:65-72 [Conf]
  12. Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi
    An Evolutionary Approach for Pareto-optimal Configurations in SOC Platforms. [Citation Graph (0, 0)][DBLP]
    VLSI-SOC, 2001, pp:157-168 [Conf]
  13. Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi
    A Genetic Bus Encoding Technique for Power Optimization of Embedded Systems. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2003, pp:21-30 [Conf]
  14. Maurizio Palesi, Shashi Kumar, Rickard Holsmark
    A Method for Router Table Compression for Application Specific Routing in Mesh Topology NoC Architectures. [Citation Graph (0, 0)][DBLP]
    SAMOS, 2006, pp:373-384 [Conf]
  15. Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi
    A Genetic Approach To Bus Encoding. [Citation Graph (0, 0)][DBLP]
    VLSI-SOC, 2003, pp:426-431 [Conf]
  16. Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi
    A Framework for Design Space Exploration of Parameterized VLSI Systems. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2002, pp:245-250 [Conf]
  17. Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi
    A Multi-objective Genetic Approach to Mapping Problem on Network-on-Chip. [Citation Graph (0, 0)][DBLP]
    J. UCS, 2006, v:12, n:4, pp:370-394 [Journal]
  18. Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi
    A multiobjective genetic approach for system-level exploration in parameterized systems-on-a-chip. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:4, pp:635-645 [Journal]
  19. Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi
    A GA-based design space exploration framework for parameterized system-on-a-chip platforms. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Evolutionary Computation, 2004, v:8, n:4, pp:329-346 [Journal]
  20. Maurizio Palesi, Shashi Kumar, Rickard Holsmark, Vincenzo Catania
    Exploiting Communication Concurrency for Efficient Deadlock Free Routing in Reconfigurable NoC Platforms. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2007, pp:1-8 [Conf]
  21. Giuseppe Ascia, Vincenzo Catania, Alessandro G. Di Nuovo, Maurizio Palesi, Davide Patti
    An Efficent Hierachical Fuzzy Approach for System Level System-on-a-Chip Design. [Citation Graph (0, 0)][DBLP]
    ICSAMOS, 2006, pp:115-122 [Conf]
  22. Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi
    An evolutionary approach to network-on-chip mapping problem. [Citation Graph (0, 0)][DBLP]
    Congress on Evolutionary Computation, 2005, pp:112-119 [Conf]
  23. Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi, Antonio Parlato
    An evolutionary approach for reducing the energy in address buses. [Citation Graph (0, 0)][DBLP]
    ISICT, 2003, pp:76-81 [Conf]
  24. Giuseppe Ascia, Vincenzo Catania, Alessandro G. Di Nuovo, Maurizio Palesi, Davide Patti
    Efficient design space exploration for application specific systems-on-a-chip. [Citation Graph (0, 0)][DBLP]
    Journal of Systems Architecture, 2007, v:53, n:10, pp:733-750 [Journal]

  25. High Performance Computing for Embedded System Design: A Case Study. [Citation Graph (, )][DBLP]


  26. Efficient Application Specific Routing Algorithms for NoC Systems utilizing Partially Faulty Links. [Citation Graph (, )][DBLP]


  27. An Effective Methodology to Multi-objective Design of Application Domain-specific Embedded Architectures. [Citation Graph (, )][DBLP]


  28. Data Encoding for Low-Power in Wormhole-Switched Networks-on-Chip. [Citation Graph (, )][DBLP]


  29. Neighbors-on-Path: A New Selection Strategy for On-Chip Networks. [Citation Graph (, )][DBLP]


  30. A Communication-Aware Topological Mapping Technique for NoCs. [Citation Graph (, )][DBLP]


  31. Multi-Objective Evolutionary Fuzzy Clustering for High-Dimensional Problems. [Citation Graph (, )][DBLP]


  32. A multi-objective strategy for concurrent mapping and routing in networks on chip. [Citation Graph (, )][DBLP]


  33. Hyperblock formation: a power/energy perspective for high performance VLIW architectures. [Citation Graph (, )][DBLP]


  34. Design of Bandwidth Aware and Congestion Avoiding Efficient Routing Algorithms for Networks-on-Chip Platforms. [Citation Graph (, )][DBLP]


  35. HiRA: A methodology for deadlock free routing in hierarchical networks on chip. [Citation Graph (, )][DBLP]


  36. An evolutionary approach for reducing the switching activity in address buses. [Citation Graph (, )][DBLP]


  37. An Hybrid Soft Computing Approach for Automated Computer Design. [Citation Graph (, )][DBLP]


  38. Performance evaluation of efficient multi-objective evolutionary algorithms for design space exploration of embedded computer systems. [Citation Graph (, )][DBLP]


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