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Yusuf Leblebici: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Sorin Cotofana, Alexandre Schmid, Yusuf Leblebici, A. Ionescu, Oliver Soffke, Peter Zipf, Manfred Glesner, A. Rubio
    CONAN - A Design Exploration Framework for Reliable Nano-Electronics. [Citation Graph (0, 0)][DBLP]
    ASAP, 2005, pp:260-267 [Conf]
  2. Paul Muller, Armin Tajalli, Seyed Mojtaba Atarodi, Yusuf Leblebici
    Top-Down Design of a Low-Power Multi-Channel 2.5-Gbit/s/Channel Gated Oscillator Clock-Recovery Circuit. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:258-263 [Conf]
  3. Alexandre Schmid, Yusuf Leblebici
    A Highly Fault Tolerant PLA Architecture for Failure-Prone Nanometer CMOS and Novel Quantum Device Technologies. [Citation Graph (0, 0)][DBLP]
    DFT, 2004, pp:39-47 [Conf]
  4. Stéphane Badel, Alexandre Schmid, Yusuf Leblebici
    VLSI Realization of a Two-Dimensional Hamming Distance Comparator ANN for Image Processing Applications. [Citation Graph (0, 0)][DBLP]
    ESANN, 2003, pp:445-450 [Conf]
  5. Soner Yaldiz, Alper Demir, Serdar Tasiran, Paolo Ienne, Yusuf Leblebici
    Characterizing and Exploiting Task-Load Variability and Correlation for Energy Management in multi-core systems. [Citation Graph (0, 0)][DBLP]
    ESTImedia, 2005, pp:135-140 [Conf]
  6. Ayse Kivilcim Coskun, Tajana Simunic Rosing, Yusuf Leblebici, Giovanni De Micheli
    A simulation methodology for reliability analysis in multi-core SoCs. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2006, pp:95-99 [Conf]
  7. Milos Stanisavljevic, Frank K. Gürkaynak, Alexandre Schmid, Yusuf Leblebici, Maria Gabrani
    Design and realization of a fault-tolerant 90nm CMOS cryptographic engine capable of performing under massive defect density. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2007, pp:204-207 [Conf]
  8. Yusuf Leblebici, Sung-Mo Kang
    An Integrated Hot-Carrier Degradation Simulator for VLSI Reliability Analysis. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1990, pp:400-403 [Conf]
  9. Yung-Ho Shih, Yusuf Leblebici, Sung-Mo Kang
    New Simulation Methods for MOS VLSI Timing and Reliability. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1991, pp:162-165 [Conf]
  10. Stéphane Badel, Alexandre Schmid, Yusuf Leblebici
    Mixed analog-digital image processing circuit based on Hamming artificial neural network architecture. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2004, pp:780-783 [Conf]
  11. Turan Demirci, Ilhan Hatirnaz, Yusuf Leblebici
    Full-custom CMOS realization of a high-performance binary sorting engine with linear area-time complexity. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2003, pp:453-456 [Conf]
  12. Mehmet Derin Harmanci, Nuria Pazos Escudero, Yusuf Leblebici, Paolo Ienne
    Quantitative modelling and comparison of communication schemes to guarantee quality-of-service in networks-on-chip. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2005, pp:1782-1785 [Conf]
  13. Ilhan Hatirnaz, Yusuf Leblebici
    Modelling and implementation of twisted differential on-chip interconnects for crosstalk noise reduction. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2004, pp:185-188 [Conf]
  14. Takahide Oya, Tetsuya Asai, Yoshihito Amemiya, Alexandre Schmid, Yusuf Leblebici
    Single-electron circuit for inhibitory spiking neural network with fault-tolerant architecture. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2005, pp:2535-2538 [Conf]
  15. Alexandre Schmid, Yusuf Leblebici
    Robust and fault-tolerant circuit design for nanometer-scale devices and single-electron transistors. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2004, pp:685-688 [Conf]
  16. Zeynep Toprak Deniz, Yusuf Leblebici
    Design and realization of a modular 200 MSample/s 12-bit pipelined A/D converter block using deep-submicron digital CMOS technology. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2003, pp:841-844 [Conf]
  17. Zeynep Toprak Deniz, Yusuf Leblebici
    Low-power current mode logic for improved DPA-resistance in embedded systems. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2005, pp:1059-1062 [Conf]
  18. Ilhan Hatirnaz, Frank K. Gürkaynak, Yusuf Leblebici
    Realization of a programmable rank-order filter architecture using capacitive threshold logic gates. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 1999, pp:435-438 [Conf]
  19. Alexandre Schmid, D. Bowler, R. Baumgartner, Yusuf Leblebici
    A novel analog-digital flash converter architecture based on capacitive threshold gates. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 1999, pp:172-175 [Conf]
  20. Armin Tajalli, Paul Muller, Seyed Mojtaba Atarodi, Yusuf Leblebici
    A low-power, multichannel gated oscillator-based CDR for short-haul applications. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2005, pp:107-110 [Conf]
  21. Elizabeth J. Brauer, Yusuf Leblebici
    Low noise MCML prefix adders using 0.18 µm CMOS technology. [Citation Graph (0, 0)][DBLP]
    Circuits, Signals, and Systems, 2004, pp:467-470 [Conf]
  22. Elizabeth J. Brauer, Yusuf Leblebici
    Sub-70 PS full adder IN 0.18 µm CMOS current-mode logic. [Citation Graph (0, 0)][DBLP]
    Circuits, Signals, and Systems, 2004, pp:483-487 [Conf]
  23. Takahide Oya, Alexandre Schmid, Tetsuya Asai, Yusuf Leblebici, Yoshihito Amemiya
    On the fault tolerance of a clustered single-electron neural network for differential enhancement. [Citation Graph (0, 0)][DBLP]
    IEICE Electronic Express, 2005, v:2, n:3, pp:76-80 [Journal]
  24. Carlos H. Díaz, Sung-Mo Kang, Yusuf Leblebici
    An accurate analytical delay model for BiCMOS driver circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1991, v:10, n:5, pp:577-588 [Journal]
  25. Yusuf Leblebici, Sung-Mo Kang
    Modeling of nMOS transistors for simulation of hot-carrier-induced device and circuit degradation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1992, v:11, n:2, pp:235-246 [Journal]
  26. Yung-Ho Shih, Yusuf Leblebici, Sung-Mo Kang
    ILLIADS: a fast timing and reliability simulator for digital MOS circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1993, v:12, n:9, pp:1387-1402 [Journal]
  27. Alexandre Schmid, Yusuf Leblebici
    Robust circuit and system design methodologies for nanometer-scale devices and single-electron transistors. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2004, v:12, n:11, pp:1156-1166 [Journal]
  28. Stéphane Badel, Yusuf Leblebici
    Breaking the Power-Delay Tradeoff: Design of Low-Power High-Speed MOS Current-Mode Logic Circuits Operating with Reduced Supply Voltage. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:1871-1874 [Conf]
  29. O. C. Akgun, Yusuf Leblebici
    Weak inversion performance of CMOS and DCVSPG logic families in sub-300 mV range. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]
  30. Elizabeth J. Brauer, Ilhan Hatirnaz, Stéphane Badel, Yusuf Leblebici
    Via-programmable expanded universal logic gate in MCML for structured ASIC applications: circuit design. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]
  31. Armin Tajalli, Paul Muller, Seyed Mojtaba Atarodi, Yusuf Leblebici
    Analysis and modeling of jitter and frequency tolerance in gated oscillator based CDRs. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]
  32. Francesco Regazzoni, Stéphane Badel, Thomas Eisenbarth, Johann Großschädl, Axel Poschmann, Zeynep Toprak Deniz, Marco Macchetti, Laura Pozzi, Christof Paar, Yusuf Leblebici, Paolo Ienne
    A Simulation-Based Methodology for Evaluating the DPA-Resistance of Cryptographic Functional Units with Application to CMOS and MCML Technologies. [Citation Graph (0, 0)][DBLP]
    ICSAMOS, 2007, pp:209-214 [Conf]
  33. Ilhan Hatirnaz, Stéphane Badel, Nuria Pazos, Yusuf Leblebici, Srinivasan Murali, David Atienza, Giovanni De Micheli
    Early wire characterization for predictable network-on-chip global interconnects. [Citation Graph (0, 0)][DBLP]
    SLIP, 2007, pp:57-64 [Conf]
  34. Zeynep Toprak Deniz, Yusuf Leblebici, Eric A. Vittoz
    Configurable On-Line Global Energy Optimization in Multi-Core Embedded Systems Using Principles of Analog Computation. [Citation Graph (0, 0)][DBLP]
    VLSI-SoC, 2006, pp:379-384 [Conf]
  35. Milos Stanisavljevic, Alexandre Schmid, Yusuf Leblebici
    A Methodology for Reliability Enhancement of Nanometer-Scale Digital Systems Based on a-priori Functional Fault- Tolerance Analysis. [Citation Graph (0, 0)][DBLP]
    VLSI-SoC, 2005, pp:111-125 [Conf]
  36. Stéphane Badel, Ilhan Hatirnaz, Yusuf Leblebici, Elizabeth J. Brauer
    Implementation of Structured ASIC Fabric Using Via-Programmable Differential MCML Cells. [Citation Graph (0, 0)][DBLP]
    VLSI-SoC, 2006, pp:234-238 [Conf]
  37. Derin Derin Harmanci, Nuria Pazos, Paolo Ienne, Yusuf Leblebici
    A Predictable Communication Scheme for Embedded Multiprocessor Systems. [Citation Graph (0, 0)][DBLP]
    VLSI-SoC, 2006, pp:152-157 [Conf]
  38. Paul Muller, Armin Tajalli, Seyed Mojtaba Atarodi, Yusuf Leblebici
    Top-Down Design of a Low-Power Multi-Channel 2.5-Gbit/s/Channel Gated Oscillator Clock-Recovery Circuit [Citation Graph (0, 0)][DBLP]
    CoRR, 2007, v:0, n:, pp:- [Journal]
  39. Ayse Kivilcim Coskun, Tajana Simunic, Kresimir Mihic, Giovanni De Micheli, Yusuf Leblebici
    Analysis and Optimization of MPSoC Reliability. [Citation Graph (0, 0)][DBLP]
    J. Low Power Electronics, 2006, v:2, n:1, pp:56-69 [Journal]

  40. A stochastic perturbative approach to design a defect-aware thresholder in the sense amplifier of crossbar memories. [Citation Graph (, )][DBLP]


  41. Design space exploration for field programmable compressor trees. [Citation Graph (, )][DBLP]


  42. Complete nanowire crossbar framework optimized for the multi-spacer patterning technique. [Citation Graph (, )][DBLP]


  43. A Design Flow and Evaluation Framework for DPA-Resistant Instruction Set Extensions. [Citation Graph (, )][DBLP]


  44. Programmable logic circuits based on ambipolar CNFET. [Citation Graph (, )][DBLP]


  45. Decoding nanowire arrays fabricated with the multi-spacer patterning technique. [Citation Graph (, )][DBLP]


  46. Novel Front-End Circuit Architectures for Integrated Bio-Electronic Interfaces. [Citation Graph (, )][DBLP]


  47. A Generic Standard Cell Design Methodology for Differential Circuit Styles. [Citation Graph (, )][DBLP]


  48. Dynamic thermal management in 3D multicore architectures. [Citation Graph (, )][DBLP]


  49. Ultra-low power mixed-signal design platform using subthreshold source-coupled circuits. [Citation Graph (, )][DBLP]


  50. AVGS-Mux style: A novel technology and device independent technique for reducing power and compensating process variations in FPGA fabrics. [Citation Graph (, )][DBLP]


  51. Optimization of Nanoelectronic Systems Reliability Under Massive Defect Density Using Distributed R-fold Modular Redundancy (DRMR). [Citation Graph (, )][DBLP]


  52. Architectural improvements for field programmable counter arrays: enabling efficient synthesis of fast compressor trees on FPGAs. [Citation Graph (, )][DBLP]


  53. 3D configuration caching for 2D FPGAs. [Citation Graph (, )][DBLP]


  54. Using 3D integration technology to realize multi-context FPGAs. [Citation Graph (, )][DBLP]


  55. Fault-tolerant multi-level logic decoder for nanoscale crossbar memory arrays. [Citation Graph (, )][DBLP]


  56. Memory organization and data layout for instruction set extensions with architecturally visible storage. [Citation Graph (, )][DBLP]


  57. Fault-Tolerance of Robust Feed-Forward Architecture Using Single-Ended and Differential Deep-Submicron Circuits Under Massive Defect Density. [Citation Graph (, )][DBLP]


  58. Improving the power-delay product in SCL circuits using source follower output stage. [Citation Graph (, )][DBLP]


  59. Subthreshold Circuit Design for Ultra-Low-Power Applications. [Citation Graph (, )][DBLP]


  60. Reverse Vgs Static CMOS (RVGS-SCMOS); A New Technique for Dynamically Compensating the Process Variations in Sub-threshold Designs. [Citation Graph (, )][DBLP]


  61. Improving the Power-Delay Performance in Subthreshold Source-Coupled Logic Circuits. [Citation Graph (, )][DBLP]


  62. Energy Dissipation Reduction of a Cardiac Event Detector in the Sub-Vt Domain By Architectural Folding. [Citation Graph (, )][DBLP]


  63. Jitter Tolerance Analysis of Clock and Data Recovery Circuits. [Citation Graph (, )][DBLP]


  64. Optimization of Nanoelectronic Systems Reliability by Reducing Logic Depth. [Citation Graph (, )][DBLP]


  65. Through Silicon Via-Based Grid for Thermal Control in 3D Chips. [Citation Graph (, )][DBLP]


  66. CMOS compressed imaging by Random Convolution. [Citation Graph (, )][DBLP]


  67. Validation of the porous-medium approach to model interlayer-cooled 3D-chip stacks. [Citation Graph (, )][DBLP]


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