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José M. Quintana: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Maria J. Avedillo, José M. Quintana, Héctor Pettenghi
    Logic Models Supporting the Design of MOBILE-based RTD Circuits. [Citation Graph (0, 0)][DBLP]
    ASAP, 2005, pp:254-259 [Conf]
  2. José M. Quintana, Maria J. Avedillo, Maria P. Parra, José L. Huertas
    Optimum PLA folding through boolean satisfiability. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 1995, pp:- [Conf]
  3. Manuel Martínez, Maria J. Avedillo, José M. Quintana, José L. Huertas
    A Dynamic Model for the State Assignment Problem. [Citation Graph (0, 0)][DBLP]
    DATE, 1998, pp:835-839 [Conf]
  4. Manuel Martínez, Maria J. Avedillo, José M. Quintana, José L. Huertas
    An Algorithm for Face-Constrained Encoding of Symbols Using Minimum Code Length. [Citation Graph (0, 0)][DBLP]
    DATE, 1999, pp:521-525 [Conf]
  5. Manuel Martínez, Maria J. Avedillo, José M. Quintana, H. Süß, Manfred Koegst
    An Encoding Technique for Low Power CMOS Implementations of Controllers. [Citation Graph (0, 0)][DBLP]
    DATE, 2002, pp:1083- [Conf]
  6. Maria J. Avedillo, José M. Quintana
    A Threshold Logic Synthesis Tool for RTD Circuits. [Citation Graph (0, 0)][DBLP]
    DSD, 2004, pp:624-627 [Conf]
  7. José M. Quintana, Maria J. Avedillo, Juan Núñez
    Design Guides for a Correct DC Operation in RTD-based Threshold Gates. [Citation Graph (0, 0)][DBLP]
    DSD, 2006, pp:530-536 [Conf]
  8. José M. Quintana, Maria J. Avedillo, Raúl Jiménez, Esther Rodríguez-Villegas
    Practical low-cost CPL implementations threshold logic functions. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2001, pp:139-144 [Conf]
  9. Juan Núñez, José M. Quintana, Maria J. Avedillo
    Operation limits in RTD-based ternary quantizers. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2007, pp:114-119 [Conf]
  10. Valeriu Beiu, Maria J. Avedillo, José M. Quintana
    Review of Capacitive Threshold Gate Implementations. [Citation Graph (0, 0)][DBLP]
    ICANN, 2003, pp:737-744 [Conf]
  11. Maria J. Avedillo, José M. Quintana, José L. Huertas
    Robust frequency divider based on resonant tunneling devices. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2005, pp:2647-2650 [Conf]
  12. Maria J. Avedillo, José M. Quintana, José L. Huertas
    Easily Testable PLA-based FSMS. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1993, pp:1603-1606 [Conf]
  13. Juan A. Prieto, José M. Quintana, Adoración Rueda, José L. Huertas
    An Algorithm for the Place-and-Route Problem in the Layout of Analog Circuits. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1994, pp:491-494 [Conf]
  14. José M. Quintana, Maria J. Avedillo, Héctor Pettenghi
    Programmable logic gate based on resonant tunnelling devices. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2004, pp:697-700 [Conf]
  15. José M. Quintana, Maria J. Avedillo
    Reed-Muller descriptions of symmetric functions. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:682-685 [Conf]
  16. Esther Rodríguez-Villegas, Maria J. Avedillo, José M. Quintana, Gloria Huertas, Adoración Rueda
    vMOS-based sorters for multiplier implementations. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 1999, pp:338-341 [Conf]
  17. José M. Quintana, Maria J. Avedillo, José L. Huertas
    Simplified Reed-Muller expressions for residue threshold functions. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2002, pp:599-602 [Conf]
  18. Maria J. Avedillo, José M. Quintana, Esther Rodríguez-Villegas
    Simple parallel weighted order statistic filter implementations. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2002, pp:607-610 [Conf]
  19. Esther Rodríguez-Villegas, José M. Quintana, Maria J. Avedillo, Adoración Rueda
    High-speed low-power logic gates using floating gates. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2002, pp:389-392 [Conf]
  20. Valeriu Beiu, José M. Quintana, Maria J. Avedillo
    Review of Differential Threshold Gate Implementations. [Citation Graph (0, 0)][DBLP]
    Neural Networks and Computational Intelligence, 2003, pp:44-49 [Conf]
  21. Maria J. Avedillo, José M. Quintana, Raúl Jiménez-Naharro
    Pass-transistor based implementations of threshold logic gates for WOS filtering. [Citation Graph (0, 0)][DBLP]
    Microelectronics Journal, 2004, v:35, n:11, pp:869-873 [Journal]
  22. Héctor Pettenghi, Maria J. Avedillo, José M. Quintana
    Non Return Mobile Logic Family. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:125-128 [Conf]
  23. José M. Quintana, Maria J. Avedillo, Héctor Pettenghi
    Self-latching operation limits for MOBILE circuits. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]

  24. A performance-driven placement algorithm with simultaneous Place&Route optimization for analog ICs. [Citation Graph (, )][DBLP]


  25. A new method for the state reduction of incompletely specified finite sequential machines. [Citation Graph (, )][DBLP]


  26. A novel contribution to the RTD-based threshold logic family. [Citation Graph (, )][DBLP]


  27. Limits to a correct operation in RTD-based ternary inverters. [Citation Graph (, )][DBLP]


  28. Limits to a Correct Evaluation in RTD-Based Quaternary Inverters. [Citation Graph (, )][DBLP]


  29. A quasi-differential quantizer based on SMOBILE. [Citation Graph (, )][DBLP]


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