Search the dblp DataBase

Publications of Author

1. José L. Ayala, Marisa Luisa López-Vallejo, Alexander V. Veidenbaum, Carlos A. Lopez
   Energy Aware Register File Implementation through Instruction Predecode. [Citation Graph (0, 0)][DBLP]
   ASAP, 2003, pp:86-96 [Conf]
   
2. David Atienza, Praveen Raghavan, José L. Ayala, Giovanni De Micheli, Francky Catthoor, Diederik Verkest, Marisa López-Vallejo
   Compiler-Driven Leakage Energy Reduction in Banked Register Files. [Citation Graph (0, 0)][DBLP]
   PATMOS, 2006, pp:107-116 [Conf]
   
3. José L. Ayala, Marisa Luisa López-Vallejo
   A Unified Framework for Power-Aware Design of Embedded Systems. [Citation Graph (0, 0)][DBLP]
   PATMOS, 2003, pp:239-248 [Conf]
   
4. José L. Ayala, Alexander V. Veidenbaum, Marisa Luisa López-Vallejo
   Power-Aware Compilation for Register File Energy Reduction. [Citation Graph (0, 0)][DBLP]
   International Journal of Parallel Programming, 2003, v:31, n:6, pp:451-467 [Journal]
   
5. Pablo Ituero, José L. Ayala, Marisa López-Vallejo
   Leakage-based On-Chip Thermal Sensor for CMOS Technology. [Citation Graph (0, 0)][DBLP]
   ISCAS, 2007, pp:3327-3330 [Conf]
   
6. Praveen Raghavan, José L. Ayala, David Atienza, Francky Catthoor, Giovanni De Micheli, Marisa López-Vallejo
   Reduction of Register File Delay Due to Process Variability in VLIW Embedded Processors. [Citation Graph (0, 0)][DBLP]
   ISCAS, 2007, pp:121-124 [Conf]
   
7. 
   Reliability-aware design for nanometer-scale devices. [Citation Graph (, )][DBLP]
   
   
8. 
   Dynamic thermal management in 3D multicore architectures. [Citation Graph (, )][DBLP]
   
   
9. 
   Thermal-aware compilation for system-on-chip processing architectures. [Citation Graph (, )][DBLP]
   
   
10. 
    Through Silicon Via-Based Grid for Thermal Control in 3D Chips. [Citation Graph (, )][DBLP]