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Ali Afzali-Kusha: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Masoud Daneshtalab, Ashkan Sobhani, Ali Afzali-Kusha, Omid Fatemi, Zainalabedin Navabi
    NoC Hot Spot minimization Using AntNet Dynamic Routing Algorithm. [Citation Graph (0, 0)][DBLP]
    ASAP, 2006, pp:33-38 [Conf]
  2. S. H. Rasouli, A. Amirabadi, A. Seyedi, Ali Afzali-Kusha
    Double edge triggered Feedback Flip-Flop in sub 100NM technology. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2006, pp:297-302 [Conf]
  3. M. Saneei, Ali Afzali-Kusha, Zainalabedin Navabi
    Sign bit reduction encoding for low power applications. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:214-217 [Conf]
  4. Shervin Sharifi, Javid Jaffari, Mohammad Hosseinabady, Ali Afzali-Kusha, Zainalabedin Navabi
    Simultaneous Reduction of Dynamic and Static Power in Scan Structures. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:846-851 [Conf]
  5. A. Amirabadi, Javid Jaffari, Ali Afzali-Kusha, Mehrdad Nourani, Ali Khaki-Firooz
    Leakage current reduction by new technique in standby mode. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2004, pp:158-161 [Conf]
  6. Mehrdad Najibi, M. Salehi, Ali Afzali-Kusha, Massoud Pedram, Seid Mehdi Fakhraie, Hossein Pedram
    Dynamic voltage and frequency management based on variable update intervals for frequency setting. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2006, pp:755-760 [Conf]
  7. M. Maddah, Ali Afzali-Kusha, H. Soltanian-Zadeha
    Fast center-line extraction for quantification of vessels in confocal microscopy images. [Citation Graph (0, 0)][DBLP]
    ISBI, 2002, pp:461-464 [Conf]
  8. Ali Abbasian, Safar Hatami, Ali Afzali-Kusha, Mehrdad Nourani, Carco Lucas
    Event-driven dynamic power management based on wavelet forecasting theory. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2004, pp:325-328 [Conf]
  9. Ali Abbasian, S. Rasouli, Ali Afzali-Kusha, Mehrdad Nourani
    No-race charge recycling complementary pass transistor logic (NCRCPL) for low power applications. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2003, pp:289-292 [Conf]
  10. Mohammad Alisafaee, Safar Hatami, Ehsan Atoofian, Zainalabedin Navabi, Ali Afzali-Kusha
    A low-power scan-path architecture. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2005, pp:5278-5281 [Conf]
  11. B. Afkal, Ali Afzali-Kusha, Mahmoud El Nokali
    Efficient power model for crossbar interconnects. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 2005, pp:5858-5861 [Conf]
  12. Behnam Amelifard, Ali Afzali-Kusha, Ahmad Khademzadeh
    Enhancing the efficiency of cluster voltage scaling technique for low-power application. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2005, pp:1666-1669 [Conf]
  13. A. Amirabadi, Y. Mortazavi, Nariman Moezzi Madani, Ali Afzali-Kusha, Mehrdad Nourani
    Domino logic with an efficient variable threshold voltage keeper. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2005, pp:1674-1677 [Conf]
  14. Morteza Gholipour, Hamid Shojaee, Ali Afzali-Kusha, Ahmad Khademzadeh, Mehrdad Nourani
    An efficient model for performance analysis of asynchronous pipeline design methods. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2005, pp:5234-5237 [Conf]
  15. Mohammad Taherzadeh-Sani, Ali Abbasian, Behnam Amelifard, Ali Afzali-Kusha
    Modeling of MOS transistors based on genetic algorithm and simulated annealing. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 2005, pp:6218-6221 [Conf]
  16. Mohammad H. Tehranipour, Mehrdad Nourani, Seid Mehdi Fakhraie, Ali Afzali-Kusha
    Systematic test program generation for SoC testing using embedded processor. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2003, pp:541-544 [Conf]
  17. Mohammad Yavari, Omid Shoaei, Ali Afzali-Kusha
    A very low-voltage, low-power and high resolution sigma-delta modulator for digital audio in 0.25µm CMOS. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2003, pp:1045-1048 [Conf]
  18. Hamid Mahmoodi-Meimand, Ali Afzali-Kusha
    Efficient power clock generation for adiabatic logic. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:642-645 [Conf]
  19. Mohammad H. Tehranipour, Mehrdad Nourani, Karim Arabi, Ali Afzali-Kusha
    Mixed RL-Huffman encoding for power reduction and data compression in scan test. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2004, pp:681-684 [Conf]
  20. Masood Dehyadgari, Mohsen Nickray, Ali Afzali-Kusha, Zainalabedin Navabi
    A New Protocol Stack Model for Network on Chip. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2006, pp:440-441 [Conf]
  21. A. S. Seyedi, S. H. Rasouli, A. Amirabadi, Ali Afzali-Kusha
    Clock Gated Static Pulsed Flip-Flop (CGSPFF) in Sub 100 nm Technology. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2006, pp:373-377 [Conf]
  22. Vahid Moalemi, Ali Afzali-Kusha
    Subthreshold Pass Transistor Logic for Ultra-Low Power Operation. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2007, pp:490-491 [Conf]
  23. Vahid Moalemi, Ali Afzali-Kusha
    Subthreshold 1-Bit Full Adder Cells in sub-100 nm Technologies. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2007, pp:514-515 [Conf]
  24. Mohammad Azim Karami, Ali Afzali-Kusha, Reza Faraji-Dana, Masoud Rostami
    Quantitative Comparison of Optical and Electrical H, X, and Y clock Distribution Networks. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2007, pp:488-489 [Conf]
  25. Bahman Javadi, Mohsen Naderi, Hossein Pedram, Ali Afzali-Kusha, Mohammad K. Akbari
    An Asynchronous Viterbi Decoder for Low-Power Applications. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2003, pp:471-480 [Conf]
  26. Mohammad D. Mottaghi, Ali Afzali-Kusha, Zainalabedin Navabi
    ByZFAD: a low switching activity architecture for shift-and-add multipliers. [Citation Graph (0, 0)][DBLP]
    SBCCI, 2006, pp:179-183 [Conf]
  27. Masoud Daneshtalab, Ali Afzali-Kusha, Ashkan Sobhani, Zainalabedin Navabi, Mohammad D. Mottaghi, Omid Fatemi
    Ant colony based routing architecture for minimizing hot spots in NOCs. [Citation Graph (0, 0)][DBLP]
    SBCCI, 2006, pp:56-61 [Conf]
  28. R. Dehghani, Seyed Mojtaba Atarodi, B. Bornoosh, Ali Afzali-Kusha
    A Reduced Complexity 3rd Order Digital Delta-Sigma Modulator for Fractional-N Frequency Synthesis. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2004, pp:615-618 [Conf]
  29. Masoud Daneshtalab, A. Pedram, Mohammad Hossein Neishaburi, M. Riazati, Ali Afzali-Kusha, Simak Mohammadi
    Distributing Congestions in NoCs through a Dynamic Routing Algorithm based on Input and Output Selections. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2007, pp:546-550 [Conf]
  30. Davood Shahrjerdi, Bahman Hekmatshoar, Ali Khaki-Firooz, Ali Afzali-Kusha
    Optimization of the VT control method for low-power ultra-thin double-gate SOI logic circuits. [Citation Graph (0, 0)][DBLP]
    Integration, 2005, v:38, n:3, pp:505-513 [Journal]
  31. Safar Hatami, M. Yaser Azizi, Hamid-Reza Bahrami, Davoud Motavalizadeh-Naeini, Ali Afzali-Kusha
    Accurate and efficient modeling of SOI MOSFET with technology independent neural networks. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:11, pp:1580-1587 [Journal]
  32. Mostafa Savadi Oskooei, Ali Afzali-Kusha, Seyed Mojtaba Atarodi
    A High-Speed and Low-Power Voltage Controlled Oscillator in 0.18-µm CMOS Process. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:933-936 [Conf]
  33. M. Saneei, Ali Afzali-Kusha, Zainalabedin Navabi
    Low-power and low-latency cluster topology for local traffic NoCs. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]
  34. G. Razavipour, A. Motamedi, Ali Afzali-Kusha
    WL-VC SRAM: a low leakage memory circuit for deep sub-micron design. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]
  35. M. Riazati, Ashkan Sobhani, M. Mottaghi-Dastjerdi, Ali Afzali-Kusha, Ali Khakifirooz
    Low-power multiplier with static decision for input manipulation. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]
  36. A. Amirabadi, A. Chehelcheraghi, S. H. Rasouli, A. Seyedi, Ali Afzali-Kusha
    Low power and high performance clock delayed domino logic using saturated keeper. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]
  37. N. Honarmand, M. Reza Javaheri, N. Sedaghati-Mokhtari, Ali Afzali-Kusha
    Power efficient sequential multiplication using pre-computation. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]
  38. Hadi Parandeh-Afshar, Ali Afzali-Kusha, Ali Khakifirooz
    A very high performance address BUS encoder. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]
  39. B. Kheradmand-Boroujeni, F. Aezinia, Ali Afzali-Kusha
    High performance circuit techniques for dynamic OR gates. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]
  40. A. S. Seyedi, S. H. Rasouli, A. Amirabadi, Ali Afzali-Kusha
    Low power low leakage clock gated static pulsed flip-flop. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]
  41. Saeid Mehrmanesh, B. Eghbalkhah, Saeed Saeedi, Ali Afzali-Kusha, Seyed Mojtaba Atarodi
    A compact low power mixed-signal equalizer for gigabit Ethernet applications. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]
  42. Shervin Sharifi, Javid Jaffari, Mohammad Hosseinabady, Ali Afzali-Kusha, Zainalabedin Navabi
    Simultaneous Reduction of Dynamic and Static Power in Scan Structures [Citation Graph (0, 0)][DBLP]
    CoRR, 2007, v:0, n:, pp:- [Journal]
  43. A. Amirabadi, Ali Afzali-Kusha, Y. Mortazavi, Mehrdad Nourani
    Clock Delayed Domino Logic With Efficient Variable Threshold Voltage Keeper. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2007, v:15, n:2, pp:125-134 [Journal]
  44. Shervin Sharifi, Javid Jaffari, Mohammad Hosseinabady, Ali Afzali-Kusha, Zainalabedin Navabi
    Scan-Based Structure with Reduced Static and Dynamic Power Consumption. [Citation Graph (0, 0)][DBLP]
    J. Low Power Electronics, 2006, v:2, n:3, pp:477-487 [Journal]

  45. An efficent dynamic multicast routing protocol for distributing traffic in NOCs. [Citation Graph (, )][DBLP]

  46. Low-Power Low-Energy Prime-Field ECC Processor Based on Montgomery Modular Inverse Algorithm. [Citation Graph (, )][DBLP]

  47. Low Standby Power and Robust FinFET Based SRAM Design. [Citation Graph (, )][DBLP]

  48. Novel MOS Decoupling Capacitor Optimization Technique for Nanotechnologies. [Citation Graph (, )][DBLP]

  49. Stall Power Reduction in Pipelined Architecture Processors. [Citation Graph (, )][DBLP]

  50. Forecasting-Based Dynamic Virtual Channels Allocation for Power Optimization of Network-on-Chips. [Citation Graph (, )][DBLP]

  51. Negative Exponential Distribution Traffic Pattern for Power/Performance Analysis of Network on Chips. [Citation Graph (, )][DBLP]

  52. Novel High Speed and Low Power Single and Double Edge-Triggered Flip-Flops. [Citation Graph (, )][DBLP]

  53. An Efficient Clocking Scheme for On-Chip Communications. [Citation Graph (, )][DBLP]

  54. Optimizing High Speed Flip-Flop Using Genetic Algorithm. [Citation Graph (, )][DBLP]

  55. Low Power Combinational Multipliers using Data-driven Signal Gating. [Citation Graph (, )][DBLP]

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