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Steven Derrien: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Alain Darte, Steven Derrien, Tanguy Risset
    Hardware/Software Interface for Multi-Dimensional Processor Arrays. [Citation Graph (0, 0)][DBLP]
    ASAP, 2005, pp:28-35 [Conf]
  2. Dominique Lavenier, Stéphane Guyetant, Steven Derrien, Stéphane Rubini
    A Reconfigurable Parallel Disk System for Filtering Genomic Banks. [Citation Graph (0, 0)][DBLP]
    Engineering of Reconfigurable Systems and Algorithms, 2003, pp:154-166 [Conf]
  3. Steven Derrien, Sanjay V. Rajopadhye
    FCCMS and the Memory Wall. [Citation Graph (0, 0)][DBLP]
    FCCM, 2000, pp:329-330 [Conf]
  4. Steven Derrien, Sanjay V. Rajopadhye
    Loop Tiling for Reconfigurable Accelerators. [Citation Graph (0, 0)][DBLP]
    FPL, 2001, pp:398-408 [Conf]
  5. Steven Derrien, Kurt Konolige
    Approximating a Single Viewpoint in Panoramic Imaging Devices. [Citation Graph (0, 0)][DBLP]
    ICRA, 2000, pp:3931-3938 [Conf]
  6. Auguste Noumsi, Steven Derrien, Patrice Quinton
    Acceleration of a content-based image-retrieval application on the RDISK cluster. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2006, pp:- [Conf]
  7. Steven Derrien, Sanjay V. Rajopadhye, Susmita Sur-Kolay
    Combined instruction and loop parallelism in array synthesis for FPGAs. [Citation Graph (0, 0)][DBLP]
    ISSS, 2001, pp:165-170 [Conf]
  8. Sanjay V. Rajopadhye, Steven Derrien
    Energy/Power Estimation of Regular Processor Arrays. [Citation Graph (0, 0)][DBLP]
    ISSS, 2002, pp:50-55 [Conf]
  9. Steven Derrien, Sanjay V. Rajopadhye, Susmita Sur-Kolay
    Optimal Partitioning for FPGA Based Regular Array Implementations. [Citation Graph (0, 0)][DBLP]
    PARELEC, 2000, pp:155-159 [Conf]
  10. Steven Derrien, Tanguy Risset
    Interfacing compiled FPGA programs: the MMAlpha approach. [Citation Graph (0, 0)][DBLP]
    PDPTA, 2000, pp:- [Conf]
  11. Stéphane Guyetant, Mathieu Giraud, Ludovic L'Hours, Steven Derrien, Stéphane Rubini, Dominique Lavenier, Frédéric Raimbault
    Cluster of re-configurable nodes for scanning large genomic banks. [Citation Graph (0, 0)][DBLP]
    Parallel Computing, 2005, v:31, n:1, pp:73-96 [Journal]
  12. Rayan Chikhi, Steven Derrien, Auguste Noumsi, Patrice Quinton
    Combining Flash Memory and FPGAs to Efficiently Implement a Massively Parallel Algorithm for Content-Based Image Retrieval. [Citation Graph (0, 0)][DBLP]
    ARC, 2007, pp:247-258 [Conf]

  13. Parallelizing HMMER for Hardware Acceleration on FPGAs. [Citation Graph (, )][DBLP]

  14. A complete design-flow for the generation of ultra low-power WSN node architectures based on micro-tasking. [Citation Graph (, )][DBLP]

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