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Shuvra S. Bhattacharyya: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Ed F. Deprettere, Todor Stefanov, Shuvra S. Bhattacharyya, Mainak Sen
    Affine Nested Loop Programs and their Binary Parameterized Dataflow Graph Counterparts. [Citation Graph (0, 0)][DBLP]
    ASAP, 2006, pp:186-190 [Conf]
  2. Shuvra S. Bhattacharyya, Praveen K. Murthy, Edward A. Lee
    Optimized software synthesis for synchronous dataflow. [Citation Graph (0, 0)][DBLP]
    ASAP, 1997, pp:250-262 [Conf]
  3. Shuvra S. Bhattacharyya, Sundararajan Sriram, Edward A. Lee
    Minimizing Synchronization Overhead in Statically Scheduled Multiprocessor Systems. [Citation Graph (0, 0)][DBLP]
    ASAP, 1995, pp:298-309 [Conf]
  4. Shuvra S. Bhattacharyya, Sundararajan Sriram, Edward A. Lee
    Latency-constrained Resynchronization for Multiprocessor DSP Implementation. [Citation Graph (0, 0)][DBLP]
    ASAP, 1996, pp:365-380 [Conf]
  5. Mukul Khandelia, Shuvra S. Bhattacharyya
    Contention-Conscious Transaction Ordering in Embedded Multiprocessors. [Citation Graph (0, 0)][DBLP]
    ASAP, 2000, pp:276-0 [Conf]
  6. Vida Kianzad, Shuvra S. Bhattacharyya
    CHARMED: A Multi-Objective Co-Synthesis Framework for Multi-Mode Embedded Systems. [Citation Graph (0, 0)][DBLP]
    ASAP, 2004, pp:28-40 [Conf]
  7. Vida Kianzad, Shuvra S. Bhattacharyya, Gang Qu
    CASPER: An Integrated Energy-Driven Approach for Task Graph Scheduling on Distributed Embedded Systems. [Citation Graph (0, 0)][DBLP]
    ASAP, 2005, pp:191-197 [Conf]
  8. Gary Spivey, Shuvra S. Bhattacharyya, Kazuo Nakajima
    A Component Architecture for FPGA-Based, DSP System Design. [Citation Graph (0, 0)][DBLP]
    ASAP, 2002, pp:41-0 [Conf]
  9. Neal K. Bambha, Shuvra S. Bhattacharyya, Jürgen Teich, Eckart Zitzler
    Hybrid global/local search strategies for dynamic voltage scaling in embedded multiprocessors. [Citation Graph (0, 0)][DBLP]
    CODES, 2001, pp:243-248 [Conf]
  10. Dong-Ik Ko, Shuvra S. Bhattacharyya
    The pipeline decomposition tree: : an analysis tool for multiprocessor implementation of image processing applications. [Citation Graph (0, 0)][DBLP]
    CODES+ISSS, 2006, pp:52-57 [Conf]
  11. Vida Kianzad, Sankalita Saha, Jason Schlessman, Gaurav Aggarwal, Shuvra S. Bhattacharyya, Wayne Wolf, Rama Chellappa
    An architectural level design methodology for embedded face detection. [Citation Graph (0, 0)][DBLP]
    CODES+ISSS, 2005, pp:136-141 [Conf]
  12. Jürgen Teich, Eckart Zitzler, Shuvra S. Bhattacharyya
    3D exploration of software schedules for DSP algorithms. [Citation Graph (0, 0)][DBLP]
    CODES, 1999, pp:168-172 [Conf]
  13. Chia-Jui Hsu, Suren Ramasubbu, Ming-Yung Ko, José Luis Pino, Shuvra S. Bhattacharyya
    Efficient simulation of critical synchronous dataflow graphs. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:893-898 [Conf]
  14. Shaoxiong Hua, Gang Qu, Shuvra S. Bhattacharyya
    Energy reduction techniques for multimedia applications with tolerance to deadline misses. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:131-136 [Conf]
  15. Praveen K. Murthy, Shuvra S. Bhattacharyya
    Shared Memory Implementations of Synchronous Dataflow Specifications. [Citation Graph (0, 0)][DBLP]
    DATE, 2000, pp:404-410 [Conf]
  16. Ankush Varma, Shuvra S. Bhattacharyya
    Java-through-C Compilation: An Enabling Technology for Java in Embedded Systems. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:161-167 [Conf]
  17. Shaoxiong Hua, Gang Qu, Shuvra S. Bhattacharyya
    Energy-Efficient Multi-processor Implementation of Embedded Software. [Citation Graph (0, 0)][DBLP]
    EMSOFT, 2003, pp:257-273 [Conf]
  18. Neal K. Bambha, Shuvra S. Bhattacharyya
    Communication strategies for shared-bus embedded multiprocessors. [Citation Graph (0, 0)][DBLP]
    EMSOFT, 2005, pp:21-24 [Conf]
  19. Vida Kianzad, Shuvra S. Bhattacharyya
    Multiprocessor Clustering for Embedded Systems. [Citation Graph (0, 0)][DBLP]
    Euro-Par, 2001, pp:697-701 [Conf]
  20. Neal K. Bambha, Shuvra S. Bhattacharyya, Jürgen Teich, Eckart Zitzler
    Systematic Integration of Parameterized Local Search Techniques in Evolutionary Algorithms. [Citation Graph (0, 0)][DBLP]
    GECCO (2), 2004, pp:383-384 [Conf]
  21. Sankalita Saha, Chung-Ching Shen, Chia-Jui Hsu, Gaurav Aggarwal, Ashok Veeraraghavan, Alan Sussman, Shuvra S. Bhattacharyya
    Model-Based OpenMP Implementation of a 3D Facial Pose Tracking System. [Citation Graph (0, 0)][DBLP]
    ICPP Workshops, 2006, pp:66-73 [Conf]
  22. Shuvra S. Bhattacharyya, Sundararajan Sriram, Edward A. Lee
    Self-Timed Resynchronization: A Post-Optimization for Static Multiprocessor Schedules. [Citation Graph (0, 0)][DBLP]
    IPPS, 1996, pp:199-205 [Conf]
  23. Neal K. Bambha, Shuvra S. Bhattacharyya
    A Joint Power/Performance Optimization Algorithm for Multiprocessor Systems using a Period Graph Construct. [Citation Graph (0, 0)][DBLP]
    ISSS, 2000, pp:91-99 [Conf]
  24. Praveen K. Murthy, Shuvra S. Bhattacharyya
    A Buffer Merging Technique for Reducing Memory Requirements of Synchronous Dataflow Specifications. [Citation Graph (0, 0)][DBLP]
    ISSS, 1999, pp:78-84 [Conf]
  25. Neal K. Bambha, Shuvra S. Bhattacharyya, Gary Euliss
    Design Considerations for Optically Connected Systems on Chip. [Citation Graph (0, 0)][DBLP]
    IWSOC, 2003, pp:299-303 [Conf]
  26. Jürgen Teich, Eckart Zitzler, Shuvra S. Bhattacharyya
    Buffer Memory Optimization in DSP Applications - An Evolutionary Approach. [Citation Graph (0, 0)][DBLP]
    PPSN, 1998, pp:885-896 [Conf]
  27. Chia-Jui Hsu, Shuvra S. Bhattacharyya
    Porting DSP Applications across Design Tools Using the Dataflow Interchange Format. [Citation Graph (0, 0)][DBLP]
    IEEE International Workshop on Rapid System Prototyping, 2005, pp:40-46 [Conf]
  28. Shaoxiong Hua, Gang Qu, Shuvra S. Bhattacharyya
    Exploring the Probabilistic Design Space of Multimedia Systems. [Citation Graph (0, 0)][DBLP]
    IEEE International Workshop on Rapid System Prototyping, 2003, pp:233-0 [Conf]
  29. Bishnupriya Bhattacharya, Shuvra S. Bhattacharyya
    Quasi-Static Scheduling of Reconfigurable Dataflow Graphs for DSP Systems. [Citation Graph (0, 0)][DBLP]
    IEEE International Workshop on Rapid System Prototyping, 2000, pp:84-89 [Conf]
  30. Dong-Ik Ko, Chung-Ching Shen, Shuvra S. Bhattacharyya, Neil Goldsman
    Energy-Driven Partitioning of Signal Processing Algorithms in Sensor Networks. [Citation Graph (0, 0)][DBLP]
    SAMOS, 2006, pp:142-154 [Conf]
  31. Bishnupriya Bhattacharya, Shuvra S. Bhattacharyya
    Consistency Analysis of Reconfigurable Dataflow Specifications. [Citation Graph (0, 0)][DBLP]
    Embedded Processor Design Challenges, 2002, pp:1-17 [Conf]
  32. Chia-Jui Hsu, Fuat Keceli, Ming-Yung Ko, Shahrooz Shahparnia, Shuvra S. Bhattacharyya
    DIF: An Interchange Format for Dataflow-Based Design Tools. [Citation Graph (0, 0)][DBLP]
    SAMOS, 2004, pp:423-432 [Conf]
  33. Jürgen Teich, Shuvra S. Bhattacharyya
    Analysis of Dataflow Programs with Interval-Limited Data-Rates. [Citation Graph (0, 0)][DBLP]
    SAMOS, 2004, pp:507-518 [Conf]
  34. Chia-Jui Hsu, Shuvra S. Bhattacharyya
    Software Synthesis from the Dataflow Interchange Format. [Citation Graph (0, 0)][DBLP]
    SCOPES, 2005, pp:37-49 [Conf]
  35. Ming-Yung Ko, Shuvra S. Bhattacharyya
    Partitioning for DSP Software Synthesis. [Citation Graph (0, 0)][DBLP]
    SCOPES, 2003, pp:344-358 [Conf]
  36. Ming-Yung Ko, Praveen K. Murthy, Shuvra S. Bhattacharyya
    Compact Procedural Implementation in DSP Software Synthesis Through Recursive Graph Decomposition. [Citation Graph (0, 0)][DBLP]
    SCOPES, 2004, pp:47-61 [Conf]
  37. Sean Leventhal, Lin Yuan, Neal K. Bambha, Shuvra S. Bhattacharyya, Gang Qu
    DSP Address Optimization Using Evolutionary Algorithms. [Citation Graph (0, 0)][DBLP]
    SCOPES, 2005, pp:91-98 [Conf]
  38. Jörg Henkel, Xiaobo Hu, Shuvra S. Bhattacharyya
    Guest Editors' Introduction: Taking on the Embedded System Design Challenge. [Citation Graph (0, 0)][DBLP]
    IEEE Computer, 2003, v:36, n:4, pp:35-37 [Journal]
  39. Shuvra S. Bhattacharyya, Edward A. Lee
    Looped Schedules for Dataflow Descriptions of Multirate Signal Processing Algorithms. [Citation Graph (0, 0)][DBLP]
    Formal Methods in System Design, 1994, v:5, n:3, pp:183-205 [Journal]
  40. Praveen K. Murthy, Shuvra S. Bhattacharyya, Edward A. Lee
    Joint Minimization of Code and Data for Synchronous Dataflow Programs. [Citation Graph (0, 0)][DBLP]
    Formal Methods in System Design, 1997, v:11, n:1, pp:41-70 [Journal]
  41. Praveen K. Murthy, Shuvra S. Bhattacharyya
    Shared buffer implementations of signal processing systems usinglifetime analysis techniques. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2001, v:20, n:2, pp:177-198 [Journal]
  42. Neal K. Bambha, Shuvra S. Bhattacharyya, Jürgen Teich, Eckart Zitzler
    Systematic integration of parameterized local search into evolutionary algorithms. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Evolutionary Computation, 2004, v:8, n:2, pp:137-155 [Journal]
  43. Bruce L. Jacob, Shuvra S. Bhattacharyya
    Introduction to the two special issues on memory. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Embedded Comput. Syst., 2002, v:1, n:1, pp:2-5 [Journal]
  44. Shaoxiong Hua, Gang Qu, Shuvra S. Bhattacharyya
    Energy-efficient embedded software implementation on multiprocessor system-on-chip with multiple voltages. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Embedded Comput. Syst., 2006, v:5, n:2, pp:321-341 [Journal]
  45. Bruce L. Jacob, Shuvra S. Bhattacharyya
    Introduction to the two special issues on memory. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Embedded Comput. Syst., 2003, v:2, n:1, pp:1-4 [Journal]
  46. Praveen K. Murthy, Shuvra S. Bhattacharyya
    Buffer merging - a powerful technique for reducing memory requirements of synchronous dataflow specifications. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2004, v:9, n:2, pp:212-237 [Journal]
  47. Neal K. Bambha, Shuvra S. Bhattacharyya
    Joint Application Mapping/Interconnect Synthesis Techniques for Embedded Chip-Scale Multiprocessors. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Parallel Distrib. Syst., 2005, v:16, n:2, pp:99-112 [Journal]
  48. Vida Kianzad, Shuvra S. Bhattacharyya
    Efficient Techniques for Clustering and Scheduling onto Embedded Multiprocessors. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Parallel Distrib. Syst., 2006, v:17, n:7, pp:667-680 [Journal]
  49. Chung-Ching Shen, Roni Kupershtok, Bo Yang, Felice Maria Vanin, Xi Shao, Datta Sheth, Neil Goldsman, Quirino Balzano, Shuvra S. Bhattacharyya
    Compact, Low Power Wireless Sensor Network System for Line Crossing Recognition. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:2506-2509 [Conf]
  50. Ming-Yung Ko, Chung-Ching Shen, Shuvra S. Bhattacharyya
    Memory-constrained Block Processing Optimization for Synthesis of DSP Software. [Citation Graph (0, 0)][DBLP]
    ICSAMOS, 2006, pp:137-143 [Conf]
  51. Ming-Yung Ko, Praveen K. Murthy, Shuvra S. Bhattacharyya
    Beyond single-appearance schedules: Efficient DSP software synthesis using nested procedure calls. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Embedded Comput. Syst., 2007, v:6, n:2, pp:- [Journal]
  52. Shaoxiong Hua, Gang Qu, Shuvra S. Bhattacharyya
    Probabilistic design of multimedia embedded systems. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Embedded Comput. Syst., 2007, v:6, n:3, pp:- [Journal]
  53. Chia-Jui Hsu, Ming-Yung Ko, Shuvra S. Bhattacharyya, Suren Ramasubbu, José Luis Pino
    Efficient simulation of critical synchronous dataflow graphs. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2007, v:12, n:3, pp:- [Journal]
  54. Jürgen Teich, Shuvra S. Bhattacharyya
    Analysis of Dataflow Programs with Interval-limited Data-rates. [Citation Graph (0, 0)][DBLP]
    VLSI Signal Processing, 2006, v:43, n:2-3, pp:247-258 [Journal]

  55. Multithreaded simulation for synchronous dataflow graphs. [Citation Graph (, )][DBLP]


  56. Mode grouping for more effective generalized scheduling of dynamic dataflow applications. [Citation Graph (, )][DBLP]


  57. An Optimized Message Passing Framework for Parallel Implementation of Signal Processing Applications. [Citation Graph (, )][DBLP]


  58. A generalized scheduling approach for dynamic dataflow applications. [Citation Graph (, )][DBLP]


  59. A generalized static data flow clustering algorithm for mpsoc scheduling of multimedia applications. [Citation Graph (, )][DBLP]


  60. A Communication Interface for Multiprocessor Signal Processing Systems. [Citation Graph (, )][DBLP]


  61. Multiobjective Optimization of FPGA-Based Medical Image Registration. [Citation Graph (, )][DBLP]


  62. Design Techniques for Streamlined Integration and Fault Tolerance in a Distributed Sensor System for Line-crossing Recognition. [Citation Graph (, )][DBLP]


  63. An Extended Motion-Estimation Architecture Applied to Shape Recognition. [Citation Graph (, )][DBLP]


  64. Design and optimization of a distributed, embedded speech recognition system. [Citation Graph (, )][DBLP]


  65. Functional DIF for Rapid Prototyping. [Citation Graph (, )][DBLP]


  66. High-Performance Buffer Mapping to Exploit DRAM Concurrency in Multiprocessor DSP Systems. [Citation Graph (, )][DBLP]


  67. An Energy-Driven Design Methodology for Distributing DSP Applications across Wireless Sensor Networks. [Citation Graph (, )][DBLP]


  68. Heterogeneous Design in Functional DIF. [Citation Graph (, )][DBLP]


  69. Improving the performance of active set based Model Predictive Controls by dataflow methods. [Citation Graph (, )][DBLP]


  70. Synthesis of DSP Architectures Using Libraries of Coarse-Grain Configurations. [Citation Graph (, )][DBLP]


  71. Low-Overhead Run-Time Scheduling for Fine-Grained Acceleration of Signal Processing Systems. [Citation Graph (, )][DBLP]


  72. Configuration and Representation of Large-Scale Dataflow Graphs using the Dataflow Interchange Format. [Citation Graph (, )][DBLP]


  73. Interface-based hierarchy for synchronous data-flow graphs. [Citation Graph (, )][DBLP]


  74. Parameterized design framework for hardware implementation of particle filters. [Citation Graph (, )][DBLP]


  75. Systematic generation of FPGA-based FFT implementations. [Citation Graph (, )][DBLP]


  76. Exploiting statically schedulable regions in dataflow programs. [Citation Graph (, )][DBLP]


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