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Valeriu Beiu: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Valeriu Beiu
    A Novel Highly Reliable Low-Power Nano Architecture When von Neumann Augments. [Citation Graph (0, 0)][DBLP]
    ASAP, 2004, pp:167-177 [Conf]
  2. Valeriu Beiu, Snorre Aunet, Jabulani Nyathi, Ray Robert Rydberg III, Asbjørn Djupdal
    On the Advantages of Serial Architectures for Low-Power Reliable Computations. [Citation Graph (0, 0)][DBLP]
    ASAP, 2005, pp:276-281 [Conf]
  3. Valeriu Beiu, Mawahib Sulieman
    Optimal Practical Perceptron Addition Application to Single Electron Technology. [Citation Graph (0, 0)][DBLP]
    ESA/VLSI, 2004, pp:541-550 [Conf]
  4. David J. Betowski, Daniel Dwyer, Valeriu Beiu
    A Novel Segmented Parabolic Sine Approximation for Direct Digital Frequency Synthesizers. [Citation Graph (0, 0)][DBLP]
    ESA/VLSI, 2004, pp:523-529 [Conf]
  5. V. Beiu, W. Ibrahim, Y. A. Alkhawwar, M. H. Sulieman
    Gate Failures Effectively Shape Multiplexing. [Citation Graph (0, 0)][DBLP]
    DFT, 2006, pp:29-40 [Conf]
  6. Valeriu Beiu
    Enhanced lower entropy bounds with application to constructive learning. [Citation Graph (0, 0)][DBLP]
    EUROMICRO, 1997, pp:541-548 [Conf]
  7. Valeriu Beiu
    Constructive Threshold Logic Addition A Synopsis of the Last Decade. [Citation Graph (0, 0)][DBLP]
    ICANN, 2003, pp:745-752 [Conf]
  8. Valeriu Beiu, Maria J. Avedillo, José M. Quintana
    Review of Capacitive Threshold Gate Implementations. [Citation Graph (0, 0)][DBLP]
    ICANN, 2003, pp:737-744 [Conf]
  9. Mawahib Sulieman, Valeriu Beiu
    Characterization of a 16-bit threshold logic single-electron technology adder. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2004, pp:681-684 [Conf]
  10. Valeriu Beiu
    Neural Addition and Fibonacci Numbers. [Citation Graph (0, 0)][DBLP]
    IWANN (2), 1999, pp:198-207 [Conf]
  11. Valeriu Beiu, Asbjørn Djupdal, Snorre Aunet
    Ultra Low-Power Neural Inspired Addition: When Serial Might Outperform Parallel Architectures. [Citation Graph (0, 0)][DBLP]
    IWANN, 2005, pp:486-493 [Conf]
  12. Valeriu Beiu, Thierry de Pauw
    Tight Bounds on the Size of Neural Networks for Classification Problems. [Citation Graph (0, 0)][DBLP]
    IWANN, 1997, pp:743-752 [Conf]
  13. Valeriu Beiu, John G. Taylor
    Optimal Mapping of Neural Networks onto FPGA's - A New Constructive Algorithm -. [Citation Graph (0, 0)][DBLP]
    IWANN, 1995, pp:822-829 [Conf]
  14. Valeriu Beiu, Artur Zawadski, Razvan Andonie, Snorre Aunet
    Using Kolmogorov Inspired Gates for Low Power Nanoelectronics. [Citation Graph (0, 0)][DBLP]
    IWANN, 2005, pp:438-445 [Conf]
  15. Suryanarayana Tatapudi, Valeriu Beiu
    Split-Precharge Differential Noise-Immune Threshold Logic Gate (SPD-NTL). [Citation Graph (0, 0)][DBLP]
    IWANN (2), 2003, pp:49-56 [Conf]
  16. Valeriu Beiu
    2D Neural Hardware versus 3D Biological Ones. [Citation Graph (0, 0)][DBLP]
    NC, 1998, pp:36-42 [Conf]
  17. Razvan Andonie, Lucian Sasu, Valeriu Beiu
    A Modified Fuzzy ARTMAP Architecture for Incremental Learning Function Approximation. [Citation Graph (0, 0)][DBLP]
    Neural Networks and Computational Intelligence, 2003, pp:124-129 [Conf]
  18. Valeriu Beiu
    On Existential and Constructive Neural Complexity Results. [Citation Graph (0, 0)][DBLP]
    Neural Networks and Computational Intelligence, 2003, pp:63-72 [Conf]
  19. Valeriu Beiu, José M. Quintana, Maria J. Avedillo
    Review of Differential Threshold Gate Implementations. [Citation Graph (0, 0)][DBLP]
    Neural Networks and Computational Intelligence, 2003, pp:44-49 [Conf]
  20. Valeriu Beiu
    VLSI arrays implementing parallel line-drawing algorithms. [Citation Graph (0, 0)][DBLP]
    Parcella, 1988, pp:241-247 [Conf]
  21. Valeriu Beiu
    On Kolmogorov's Superpositions and Boolean Functions. [Citation Graph (0, 0)][DBLP]
    SBRN, 1998, pp:55-60 [Conf]
  22. Valeriu Beiu, Sorin Draghici, Hanna E. Makaruk
    On limited fan-in optimal neural networks. [Citation Graph (0, 0)][DBLP]
    SBRN, 1997, pp:19-30 [Conf]
  23. Valeriu Beiu, J. A. Peperstraete, Joos Vandewalle, Rudy Lauwereins
    Closse Approximations of Sigmoid Functions by Sum of Step for VLSI Implementation of Neural Networks. [Citation Graph (0, 0)][DBLP]
    Sci. Ann. Cuza Univ., 1994, v:3, n:, pp:5-34 [Journal]
  24. Valeriu Beiu
    On the circuit and VLSI complexity of threshold gate COMPARISON. [Citation Graph (0, 0)][DBLP]
    Neurocomputing, 1998, v:19, n:1-3, pp:77-98 [Journal]
  25. Valeriu Beiu, John G. Taylor
    On the Circuit Complexity of Sigmoid Feedforward Neural Networks. [Citation Graph (0, 0)][DBLP]
    Neural Networks, 1996, v:9, n:7, pp:1155-1171 [Journal]
  26. Valeriu Beiu, Sorin Draghici, Thierry de Pauw
    A Constructive Approach to Calculating Lower Entropy Bounds. [Citation Graph (0, 0)][DBLP]
    Neural Processing Letters, 1999, v:9, n:1, pp:1-12 [Journal]
  27. Valeriu Beiu, Hanna E. Makaruk
    Deeper Sparsely Nets can be Optimal. [Citation Graph (0, 0)][DBLP]
    Neural Processing Letters, 1998, v:8, n:3, pp:201-210 [Journal]
  28. Valeriu Beiu, Walid Ibrahim, Sanja Lazarova-Molnar
    What von Neumann Did Not Say About Multiplexing Beyond Gate Failures - The Gory Details. [Citation Graph (0, 0)][DBLP]
    IWANN, 2007, pp:487-496 [Conf]

  29. Femto Joule Switching for Nano Electronics. [Citation Graph (, )][DBLP]


  30. Multiplexing Schemes in Single-Electron Technology. [Citation Graph (, )][DBLP]


  31. Long Live Small Fan-in Majority Gates Their Reign Looks Like Coming! [Citation Graph (, )][DBLP]


  32. Does the brain really outperform Rent's rule? [Citation Graph (, )][DBLP]


  33. Grand Challenges of Nanoelectronics and Possible Architectural Solutions: What Do Shannon, von Neumann, Kolmogorov, and Feynman Have to do with Moore. [Citation Graph (, )][DBLP]


  34. On brain-inspired hybrid topologies for nano-architectures - a Rent's rule approach -. [Citation Graph (, )][DBLP]


  35. Reduced Interconnects in Neural Networks Using a Time Multiplexed Architecture Based on Quantum Devices. [Citation Graph (, )][DBLP]


  36. On Wires Holding a Handful of Electrons. [Citation Graph (, )][DBLP]


  37. On Two-Layer Hierarchical Networks How Does the Brain Do This? [Citation Graph (, )][DBLP]


  38. A Bayesian-Based EDA Tool for Nano-circuits Reliability Calculations. [Citation Graph (, )][DBLP]


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