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Snorre Aunet:
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Publications of Author
- Valeriu Beiu, Snorre Aunet, Jabulani Nyathi, Ray Robert Rydberg III, Asbjørn Djupdal
On the Advantages of Serial Architectures for Low-Power Reliable Computations. [Citation Graph (0, 0)][DBLP] ASAP, 2005, pp:276-281 [Conf]
- Kristian Granhaug, Snorre Aunet
Six Subthreshold Full Adder Cells Characterized in 90 nm CMOS Technology. [Citation Graph (0, 0)][DBLP] DDECS, 2006, pp:27-32 [Conf]
- Kristian Granhaug, Snorre Aunet
Improving Yield and Defect Tolerance in Multifunction Subthreshold CMOS Gates. [Citation Graph (0, 0)][DBLP] DFT, 2006, pp:20-28 [Conf]
- Snorre Aunet, Morten Hartmann
Real-Time Reconfigurable Linear Threshold Elements and Some Applications to Neural Hardware. [Citation Graph (0, 0)][DBLP] ICES, 2003, pp:365-376 [Conf]
- Yngvar Berg, Snorre Aunet, Omid Mirmotahari, Mats Høvin
Novel recharge semi-floating-gate CMOS logic for multiple-valued systems. [Citation Graph (0, 0)][DBLP] ISCAS (5), 2003, pp:193-196 [Conf]
- Yngvar Berg, Snorre Aunet, Øivind Næss, Johannes Goplen Lomsdalen, Mats Høvin
Exploiting hyperbolic functions to increase linearity in low-voltage floating-gate transconductance amplifiers. [Citation Graph (0, 0)][DBLP] ISCAS (1), 2003, pp:345-348 [Conf]
- Yngvar Berg, Snorre Aunet, Øivind Næss, Henning Gundersen, Mats Høvin
Extreme low-voltage floating-gate CMOS transconductance amplifier. [Citation Graph (0, 0)][DBLP] ISCAS (1), 2001, pp:37-40 [Conf]
- Yngvar Berg, Snorre Aunet, Øivind Næss, Mats Høvin
Floating-gate CMOS differential analog inverter for ultra low-voltage applications. [Citation Graph (0, 0)][DBLP] ISCAS (1), 2001, pp:9-12 [Conf]
- Yngvar Berg, Snorre Aunet, Øivind Næss, Mats Høvin
Exploiting sinh and tanh shaped ultra low-voltage floating-gate transconductance amplifiers to reduce harmonic distortion. [Citation Graph (0, 0)][DBLP] ISCAS (4), 2001, pp:838-841 [Conf]
- Yngvar Berg, Snorre Aunet, Øivind Næss, O. Hagen, Mats Høvin
A novel floating-gate multiple-valued CMOS full-adder. [Citation Graph (0, 0)][DBLP] ISCAS (1), 2002, pp:877-880 [Conf]
- Trond Ytterdal, Snorre Aunet
Compact low-voltage self-calibrating digital floating-gate CMOS logic circuits. [Citation Graph (0, 0)][DBLP] ISCAS (5), 2002, pp:393-396 [Conf]
- Yngvar Berg, Øivind Næss, Snorre Aunet, R. Jensen, Mats Høvin
Novel floating-gate multiple-valued signal to binary signal converters for multiple-valued CMOS logic. [Citation Graph (0, 0)][DBLP] ISCAS (5), 2002, pp:385-388 [Conf]
- Yngvar Berg, Snorre Aunet, Øivind Næss, Omid Mirmotahari
Basic Multiple-Valued Functions Using Recharge CMOS Logic. [Citation Graph (0, 0)][DBLP] ISMVL, 2004, pp:346-351 [Conf]
- Snorre Aunet, Yngvar Berg
UV-programmable Floating-Gate CMOS Linear Threshold Element "P1N3". [Citation Graph (0, 0)][DBLP] IWANN (2), 2003, pp:57-64 [Conf]
- Valeriu Beiu, Asbjørn Djupdal, Snorre Aunet
Ultra Low-Power Neural Inspired Addition: When Serial Might Outperform Parallel Architectures. [Citation Graph (0, 0)][DBLP] IWANN, 2005, pp:486-493 [Conf]
- Valeriu Beiu, Artur Zawadski, Razvan Andonie, Snorre Aunet
Using Kolmogorov Inspired Gates for Low Power Nanoelectronics. [Citation Graph (0, 0)][DBLP] IWANN, 2005, pp:438-445 [Conf]
- Jon Alfredsson, Snorre Aunet, Bengt Oelmann
Small Fan-in Floating-Gate Circuits with Application to an Improved Adder Structure. [Citation Graph (0, 0)][DBLP] VLSI Design, 2007, pp:314-317 [Conf]
- Kristian Granhaug, Snorre Aunet, Tor Sverre Lande
Body-bias regulator for ultra low power multifunction CMOS gates. [Citation Graph (0, 0)][DBLP] ISCAS, 2006, pp:- [Conf]
- Snorre Aunet, Hans Kristian Otnes Berge
Statistical Simulations for Exploring Defect Tolerance and Power Consumption for 4 Subthreshold 1-Bit Addition Circuits. [Citation Graph (0, 0)][DBLP] IWANN, 2007, pp:455-462 [Conf]
- Jon Alfredsson, Snorre Aunet
Performance of CMOS and Floating-Gate Full-Adders Circuits at Subthreshold Power Supply. [Citation Graph (0, 0)][DBLP] PATMOS, 2007, pp:536-545 [Conf]
- Yngvar Berg, Omid Mirmotahari, Snorre Aunet
Pseudo Floating-Gate Inverter with Feedback Control. [Citation Graph (0, 0)][DBLP] VLSI-SoC, 2006, pp:272-277 [Conf]
Femto Joule Switching for Nano Electronics. [Citation Graph (, )][DBLP]
Improving Circuit Security against Power Analysis Attacks with Subthreshold Operation. [Citation Graph (, )][DBLP]
Three Subthreshold Flip-Flop Cells Characterized in 90 nm and 65 nm CMOS Technology. [Citation Graph (, )][DBLP]
Fault Tolerant CMOS Logic Using Ternary Gates. [Citation Graph (, )][DBLP]
New subthreshold concepts in 65nm CMOS technology. [Citation Graph (, )][DBLP]
High Speed Ultra Low Voltage CMOS inverter. [Citation Graph (, )][DBLP]
65NM sub-threshold 11T-SRAM for ultra low voltage applications. [Citation Graph (, )][DBLP]
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