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Michalis D. Galanis: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Grigoris Dimitroulakos, Michalis D. Galanis, Costas E. Goutis
    Alleviating the Data Memory Bandwidth Bottleneck in Coarse-Grained Reconfigurable Arrays. [Citation Graph (0, 0)][DBLP]
    ASAP, 2005, pp:161-168 [Conf]
  2. Michalis D. Galanis, Grigoris Dimitroulakos, Costas E. Goutis
    Speedups from Partitioning Critical Software Parts to Coarse-Grain Reconfigurable Hardware. [Citation Graph (0, 0)][DBLP]
    ASAP, 2005, pp:50-59 [Conf]
  3. Grigoris Dimitroulakos, Michalis D. Galanis, Nikos Kostaras, Costas E. Goutis
    A unified evaluation framework for coarse grained reconfigurable array architectures. [Citation Graph (0, 0)][DBLP]
    Conf. Computing Frontiers, 2007, pp:161-172 [Conf]
  4. Michalis D. Galanis, Athanasios Milidonis, George Theodoridis, Dimitrios Soudris, Constantinos E. Goutis
    A Partitioning Methodology for Accelerating Applications in Hybrid Reconfigurable Platforms. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:247-252 [Conf]
  5. Michalis D. Galanis, Athanasios Milidonis, George Theodoridis, Dimitrios Soudris, Constantinos E. Goutis
    A Partitioning Methodology for Accelerating Applications in Hybrid Reconfigurable Platforms. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:247-252 [Conf]
  6. Michalis D. Galanis, Grigoris Dimitroulakos, Costas E. Goutis
    Accelerating Applications by Mapping Critical Kernels on Coarse-Grain Reconfigurable Hardware in Hybrid Systems. [Citation Graph (0, 0)][DBLP]
    FCCM, 2005, pp:301-302 [Conf]
  7. Michalis D. Galanis, George Theodoridis, Spyros Tragoudas, Dimitrios Soudris, Constantinos E. Goutis
    Accelerating DSP Applications on a Mixed Granularity Platform with a New Reconfigurable Coarse-Grain Data-Path. [Citation Graph (0, 0)][DBLP]
    FCCM, 2004, pp:275-276 [Conf]
  8. Michalis D. Galanis, George Theodoridis, Spyros Tragoudas, Dimitrios Soudris, Constantinos E. Goutis
    A novel coarse-grain reconfigurable data-path for accelerating DSP kernels. [Citation Graph (0, 0)][DBLP]
    FPGA, 2004, pp:252- [Conf]
  9. Grigoris Dimitroulakos, Michalis D. Galanis, Costas E. Goutis
    Performance Improvements using Coarse-Grain Reconfigurable Logic in Embedded SoCs. [Citation Graph (0, 0)][DBLP]
    FPL, 2005, pp:630-635 [Conf]
  10. Michalis D. Galanis, George Theodoridis, Spyros Tragoudas, Dimitrios Soudris, Constantinos E. Goutis
    Mapping DSP Applications to a High-Performance Reconfigurable Coarse-Grain Data-Path. [Citation Graph (0, 0)][DBLP]
    FPL, 2004, pp:868-873 [Conf]
  11. Michalis D. Galanis, Grigoris Dimitroulakos, Costas E. Goutis
    Improving performance and energy consumption in embedded microprocessor platforms with a flexible custom coprocessor data-path. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2007, pp:2-7 [Conf]
  12. Grigoris Dimitroulakos, Nikos Kostaras, Michalis D. Galanis, Costas E. Goutis
    Compiler assisted architectural exploration for coarse grained reconfigurable arrays. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2007, pp:164-167 [Conf]
  13. Grigoris Dimitroulakos, Michalis D. Galanis, Costas E. Goutis
    A Compiler Method for Memory-Conscious Mapping of Applications on Coarse-Grained Reconfigurable Architectures. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2005, pp:- [Conf]
  14. Michalis D. Galanis, Athanasios Milidonis, George Theodoridis, Dimitrios Soudris, Constantinos E. Goutis
    A Framework for Partitioning Computational Intensive Applications in Hybrid Reconfigurable Platforms. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2005, pp:- [Conf]
  15. Grigoris Dimitroulakos, Michalis D. Galanis, Constantinos E. Goutis
    Exploring the design space of an optimized compiler approach for mesh-like coarse-grained reconfigurable architectures. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2006, pp:- [Conf]
  16. Michalis D. Galanis, Grigoris Dimitroulakos, Constantinos E. Goutis
    Design flow for optimizing performance in processor systems with on-chip coarse-grain reconfigurable logic. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2006, pp:- [Conf]
  17. Michalis D. Galanis, Grigoris Dimitroulakos, Constantinos E. Goutis
    Mapping DSP applications on processor systems with coarse-grain reconfigurable hardware. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2006, pp:- [Conf]
  18. Grigoris Dimitroulakos, Michalis D. Galanis, Costas E. Goutis, Athanasios Milidonis
    A high-throughput and memory efficient 2D discrete wavelet transform hardware architecture for JPEG2000 standard. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2005, pp:472-475 [Conf]
  19. Michalis D. Galanis, Athanasios Milidonis, George Theodoridis, Dimitrios Soudris, Constantinos E. Goutis
    A methodology for partitioning DSP applications in hybrid reconfigurable systems. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2005, pp:1206-1209 [Conf]
  20. Paris Kitsos, Michalis D. Galanis, Odysseas G. Koufopavlou
    A RAM-based FPGA implementation of the 64-bit MISTY1 block cipher. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2005, pp:4641-4644 [Conf]
  21. Paris Kitsos, Michalis D. Galanis, Odysseas G. Koufopavlou
    High-speed hardware implementations of the KASUMI block cipher. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2004, pp:549-552 [Conf]
  22. Michalis D. Galanis, Grigoris Dimitroulakos, Costas E. Goutis
    Performance Gains from Partitioning Embedded Applications in Processor-FPGA SoCs. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2005, pp:247-256 [Conf]
  23. Michalis D. Galanis, George Theodoridis, Spyros Tragoudas, Dimitrios Soudris, Constantinos E. Goutis
    Mapping Computational Intensive Applications to a New Coarse-Grained Reconfigurable Data-Path. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2004, pp:652-661 [Conf]
  24. Michalis D. Galanis, George Theodoridis, Spyros Tragoudas, Dimitrios Soudris, Costas E. Goutis
    A Novel Data-Path for Accelerating DSP Kernels. [Citation Graph (0, 0)][DBLP]
    SAMOS, 2004, pp:363-372 [Conf]
  25. Athanasios Milidonis, Grigoris Dimitroulakos, Michalis D. Galanis, George Theodoridis, Constantinos E. Goutis, Francky Catthoor
    An Automated C++ Code and Data Partitioning Framework for Data Management of Data-Intensive Applications. [Citation Graph (0, 0)][DBLP]
    SCOPES, 2004, pp:122-136 [Conf]
  26. Michalis D. Galanis, Paris Kitsos, Giorgos Kostopoulos, Nicolas Sklavos, Constantinos E. Goutis
    Comparison of the Hardware Implementation of Stream Ciphers. [Citation Graph (0, 0)][DBLP]
    Int. Arab J. Inf. Technol., 2005, v:2, n:4, pp:267-274 [Journal]
  27. Grigoris Dimitroulakos, Michalis D. Galanis, Athanasios Milidonis, Constantinos E. Goutis
    A high-throughput, memory efficient architecture for computing the tile-based 2D discrete wavelet transform for the JPEG2000. [Citation Graph (0, 0)][DBLP]
    Integration, 2005, v:39, n:1, pp:1-11 [Journal]
  28. Michalis D. Galanis, George Theodoridis, Spyros Tragoudas, Constantinos E. Goutis
    A Reconfigurable Coarse-grain Data-path for Accelerating Computational Intensive Kernels. [Citation Graph (0, 0)][DBLP]
    Journal of Circuits, Systems, and Computers, 2005, v:14, n:4, pp:877-893 [Journal]
  29. Paris Kitsos, Michalis D. Galanis, Odysseas G. Koufopavlou
    An Fpga Implementation of the Gprs Encryption Algorithm 3 (gea3). [Citation Graph (0, 0)][DBLP]
    Journal of Circuits, Systems, and Computers, 2005, v:14, n:2, pp:217-232 [Journal]
  30. Michalis D. Galanis, George Theodoridis, Spyros Tragoudas, Constantinos E. Goutis
    A high-performance data path for synthesizing DSP kernels. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:6, pp:1154-1162 [Journal]
  31. Michalis D. Galanis, Grigoris Dimitroulakos, Costas E. Goutis
    Performance Improvements from Partitioning Applications to FPGA Hardware in Embedded SoCs. [Citation Graph (0, 0)][DBLP]
    The Journal of Supercomputing, 2006, v:35, n:2, pp:185-199 [Journal]
  32. Michalis D. Galanis, Grigoris Dimitroulakos, Costas E. Goutis
    Partitioning Methodology for Heterogeneous Reconfigurable Functional Units. [Citation Graph (0, 0)][DBLP]
    The Journal of Supercomputing, 2006, v:38, n:1, pp:17-34 [Journal]
  33. Michalis D. Galanis, Grigoris Dimitroulakos, Costas E. Goutis
    Exploring the speedups of embedded microprocessor systems utilizing a high-performance coprocessor data-path. [Citation Graph (0, 0)][DBLP]
    The Journal of Supercomputing, 2007, v:39, n:3, pp:251-271 [Journal]
  34. Michalis D. Galanis, Athanasios Milidonis, George Theodoridis, Dimitrios Soudris, Constantinos E. Goutis
    Automated framework for partitioning DSP applications in hybrid reconfigurable platforms. [Citation Graph (0, 0)][DBLP]
    Microprocessors and Microsystems, 2007, v:31, n:1, pp:1-14 [Journal]
  35. Michalis D. Galanis, Athanasios Milidonis, Athanasios Kakarountas, Costas E. Goutis
    A design flow for speeding-up dsp applications in heterogeneous reconfigurable systems. [Citation Graph (0, 0)][DBLP]
    Microelectronics Journal, 2006, v:37, n:6, pp:554-564 [Journal]
  36. Michalis D. Galanis, Grigoris Dimitroulakos, Costas E. Goutis
    Speedups and Energy Savings of Microprocessor Platforms with a Coarse-Grained Reconfigurable Data-Path. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2007, pp:1-8 [Conf]
  37. Grigoris Dimitroulakos, Michalis D. Galanis, Constantinos E. Goutis
    Resource constrained modulo scheduling for coarse-grained reconfigurable arrays. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]
  38. Michalis D. Galanis, Grigoris Dimitroulakos, Constantinos E. Goutis
    Mapping DSP applications on processor/coarse-grain reconfigurable array architectures. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]
  39. Michalis D. Galanis, Grigoris Dimitroulakos, Costas E. Goutis
    Performance Optimization of Embedded Applications in a Hybrid Reconfigurable Platform. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2007, pp:352-362 [Conf]
  40. Michalis D. Galanis, Gregory Dimitroulakos, Costas E. Goutis
    Performance Improvements in Microprocessor Systems Utilizing a Copressor Data-Path. [Citation Graph (0, 0)][DBLP]
    ICSAMOS, 2006, pp:85-92 [Conf]
  41. Michalis D. Galanis, Athanasios Milidonis, George Theodoridis, Dimitrios Soudris, Constantinos E. Goutis
    A Partitioning Methodology for Accelerating Applications in Hybrid Reconfigurable Platforms [Citation Graph (0, 0)][DBLP]
    CoRR, 2007, v:0, n:, pp:- [Journal]
  42. Grigoris Dimitroulakos, Michalis D. Galanis, Costas E. Goutis
    Design space exploration of an optimized compiler approach for a generic reconfigurable array architecture. [Citation Graph (0, 0)][DBLP]
    The Journal of Supercomputing, 2007, v:40, n:2, pp:127-157 [Journal]
  43. Michalis D. Galanis, Gregory Dimitroulakos, Spyros Tragoudas, Costas E. Goutis
    Speedups in embedded systems with a high-performance coprocessor datapath. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2007, v:12, n:3, pp:- [Journal]
  44. Paris Kitsos, Nicolas Sklavos, Michalis D. Galanis, Odysseas G. Koufopavlou
    64-bit Block ciphers: hardware implementations and comparison analysis. [Citation Graph (0, 0)][DBLP]
    Computers & Electrical Engineering, 2004, v:30, n:8, pp:593-604 [Journal]

  45. An automated methodology for memory-conscious mapping of DSP applications on coarse-grain reconfigurable arrays. [Citation Graph (, )][DBLP]


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