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Costas E. Goutis: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Grigoris Dimitroulakos, Michalis D. Galanis, Costas E. Goutis
    Alleviating the Data Memory Bandwidth Bottleneck in Coarse-Grained Reconfigurable Arrays. [Citation Graph (0, 0)][DBLP]
    ASAP, 2005, pp:161-168 [Conf]
  2. Michalis D. Galanis, Grigoris Dimitroulakos, Costas E. Goutis
    Speedups from Partitioning Critical Software Parts to Coarse-Grain Reconfigurable Hardware. [Citation Graph (0, 0)][DBLP]
    ASAP, 2005, pp:50-59 [Conf]
  3. Grigoris Dimitroulakos, Michalis D. Galanis, Nikos Kostaras, Costas E. Goutis
    A unified evaluation framework for coarse grained reconfigurable array architectures. [Citation Graph (0, 0)][DBLP]
    Conf. Computing Frontiers, 2007, pp:161-172 [Conf]
  4. Michalis D. Galanis, Grigoris Dimitroulakos, Costas E. Goutis
    Accelerating Applications by Mapping Critical Kernels on Coarse-Grain Reconfigurable Hardware in Hybrid Systems. [Citation Graph (0, 0)][DBLP]
    FCCM, 2005, pp:301-302 [Conf]
  5. Grigoris Dimitroulakos, Michalis D. Galanis, Costas E. Goutis
    Performance Improvements using Coarse-Grain Reconfigurable Logic in Embedded SoCs. [Citation Graph (0, 0)][DBLP]
    FPL, 2005, pp:630-635 [Conf]
  6. Michalis D. Galanis, Grigoris Dimitroulakos, Costas E. Goutis
    Improving performance and energy consumption in embedded microprocessor platforms with a flexible custom coprocessor data-path. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2007, pp:2-7 [Conf]
  7. Grigoris Dimitroulakos, Nikos Kostaras, Michalis D. Galanis, Costas E. Goutis
    Compiler assisted architectural exploration for coarse grained reconfigurable arrays. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2007, pp:164-167 [Conf]
  8. Yiannis Andreopoulos, Nikolaos D. Zervas, Gauthier Lafruit, Peter Schelkens, Thanos Stouraitis, Costas E. Goutis, Jan Cornelis
    A local wavelet transform implementation versus an optimal row-column algorithm for the 2D multilevel decomposition. [Citation Graph (0, 0)][DBLP]
    ICIP (3), 2001, pp:330-333 [Conf]
  9. Grigoris Dimitroulakos, Michalis D. Galanis, Costas E. Goutis
    A Compiler Method for Memory-Conscious Mapping of Applications on Coarse-Grained Reconfigurable Architectures. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2005, pp:- [Conf]
  10. Grigoris Dimitroulakos, Michalis D. Galanis, Costas E. Goutis, Athanasios Milidonis
    A high-throughput and memory efficient 2D discrete wavelet transform hardware architecture for JPEG2000 standard. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2005, pp:472-475 [Conf]
  11. Michalis D. Galanis, Grigoris Dimitroulakos, Costas E. Goutis
    Performance Gains from Partitioning Embedded Applications in Processor-FPGA SoCs. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2005, pp:247-256 [Conf]
  12. Haralambos Michail, Athanasios Kakarountas, George N. Selimis, Costas E. Goutis
    Optimizing SHA-1 Hash Function for High Throughput with a Partial Unrolling Study. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2005, pp:591-600 [Conf]
  13. Michalis D. Galanis, George Theodoridis, Spyros Tragoudas, Dimitrios Soudris, Costas E. Goutis
    A Novel Data-Path for Accelerating DSP Kernels. [Citation Graph (0, 0)][DBLP]
    SAMOS, 2004, pp:363-372 [Conf]
  14. Nikolaos D. Zervas, Giorgos P. Anagnostopoulos, Vassilis Spiliotopoulos, Yiannis Andreopoulos, Costas E. Goutis
    Evaluation of design alternatives for the 2-D-discrete wavelet transform. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Circuits Syst. Video Techn., 2001, v:11, n:12, pp:1246-1262 [Journal]
  15. Michalis D. Galanis, Grigoris Dimitroulakos, Costas E. Goutis
    Performance Improvements from Partitioning Applications to FPGA Hardware in Embedded SoCs. [Citation Graph (0, 0)][DBLP]
    The Journal of Supercomputing, 2006, v:35, n:2, pp:185-199 [Journal]
  16. Athanasios Kakarountas, Haralambos Michail, Athanasios Milidonis, Costas E. Goutis, George Theodoridis
    High-Speed FPGA Implementation of Secure Hash Algorithm for IPSec and VPN Applications. [Citation Graph (0, 0)][DBLP]
    The Journal of Supercomputing, 2006, v:37, n:2, pp:179-195 [Journal]
  17. Michalis D. Galanis, Grigoris Dimitroulakos, Costas E. Goutis
    Partitioning Methodology for Heterogeneous Reconfigurable Functional Units. [Citation Graph (0, 0)][DBLP]
    The Journal of Supercomputing, 2006, v:38, n:1, pp:17-34 [Journal]
  18. Michalis D. Galanis, Grigoris Dimitroulakos, Costas E. Goutis
    Exploring the speedups of embedded microprocessor systems utilizing a high-performance coprocessor data-path. [Citation Graph (0, 0)][DBLP]
    The Journal of Supercomputing, 2007, v:39, n:3, pp:251-271 [Journal]
  19. Michalis D. Galanis, Athanasios Milidonis, Athanasios Kakarountas, Costas E. Goutis
    A design flow for speeding-up dsp applications in heterogeneous reconfigurable systems. [Citation Graph (0, 0)][DBLP]
    Microelectronics Journal, 2006, v:37, n:6, pp:554-564 [Journal]
  20. Michalis D. Galanis, Grigoris Dimitroulakos, Costas E. Goutis
    Speedups and Energy Savings of Microprocessor Platforms with a Coarse-Grained Reconfigurable Data-Path. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2007, pp:1-8 [Conf]
  21. Michalis D. Galanis, Grigoris Dimitroulakos, Costas E. Goutis
    Performance Optimization of Embedded Applications in a Hybrid Reconfigurable Platform. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2007, pp:352-362 [Conf]
  22. Michalis D. Galanis, Gregory Dimitroulakos, Costas E. Goutis
    Performance Improvements in Microprocessor Systems Utilizing a Copressor Data-Path. [Citation Graph (0, 0)][DBLP]
    ICSAMOS, 2006, pp:85-92 [Conf]
  23. Grigoris Dimitroulakos, Michalis D. Galanis, Costas E. Goutis
    Design space exploration of an optimized compiler approach for a generic reconfigurable array architecture. [Citation Graph (0, 0)][DBLP]
    The Journal of Supercomputing, 2007, v:40, n:2, pp:127-157 [Journal]
  24. Michalis D. Galanis, Gregory Dimitroulakos, Spyros Tragoudas, Costas E. Goutis
    Speedups in embedded systems with a high-performance coprocessor datapath. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2007, v:12, n:3, pp:- [Journal]

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