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Publications of Author

1. Jean-Luc Beuchat, Jean-Michel Muller
   Multiplication Algorithms for Radix-2 RN-Codings and Two's Complement Multiplication Algorithms for Radix-2 RN-Codings and Two's Complement. [Citation Graph (0, 0)][DBLP]
   ASAP, 2005, pp:303-308 [Conf]
   
2. Jacques-Olivier Haenni, Jean-Luc Beuchat, Eduardo Sanchez
   RENCO: A Reconfigurable Network Computer. [Citation Graph (0, 0)][DBLP]
   FCCM, 1998, pp:288-289 [Conf]
   
3. Jean-Luc Beuchat
   FPGA Implementations of the RC6 Block Cipher. [Citation Graph (0, 0)][DBLP]
   FPL, 2003, pp:101-110 [Conf]
   
4. Jean-Luc Beuchat, Arnaud Tisserand
   Small Multiplier-Based Multiplication and Division Operators for Virtex-II Devices. [Citation Graph (0, 0)][DBLP]
   FPL, 2002, pp:513-522 [Conf]
   
5. Jean-Luc Beuchat
   Some Modular Adders and Multipliers for Field Programmable Gate Arrays. [Citation Graph (0, 0)][DBLP]
   IPDPS, 2003, pp:190- [Conf]
   
6. Jean-Luc Beuchat, Jacques-Olivier Haenni, Eduardo Sanchez
   Hardware Reconfigurable Neural Networks. [Citation Graph (0, 0)][DBLP]
   IPPS/SPDP Workshops, 1998, pp:91-98 [Conf]
   
7. Jean-Luc Beuchat, Eduardo Sanchez
   An On-Line Arithmetic-Based Reconfigurable Neuroprocessor. [Citation Graph (0, 0)][DBLP]
   IPPS/SPDP Workshops, 1999, pp:700-702 [Conf]
   
8. Jean-Luc Beuchat, Eduardo Sanchez
   Using On-Line Arithmetic and Reconfiguration for Neuroprocessor Implementations. [Citation Graph (0, 0)][DBLP]
   IWANN (2), 1999, pp:129-138 [Conf]
   
9. Eduardo Sanchez, Moshe Sipper, Jacques-Olivier Haenni, Jean-Luc Beuchat, André Stauffer, Andrés Pérez-Uribe
   Static and Dynamic Configurable Systems. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. Computers, 1999, v:48, n:6, pp:556-564 [Journal]
   
10. Jean-Luc Beuchat, Jacques-Olivier Haenni, Héctor Fabio Restrepo, Christof Teuscher, Francesco J. Gómez, Eduardo Sanchez
    Approches matérielles et logicielles de l'algorithme de chiffrement IDEA. [Citation Graph (0, 0)][DBLP]
    Technique et Science Informatiques, 2002, v:21, n:2, pp:203-224 [Journal]
    
11. Jean-Luc Beuchat, Arnaud Tisserand
    Évaluation polynomiale en-ligne de fonctions élémentaires sur FPGA. [Citation Graph (0, 0)][DBLP]
    Technique et Science Informatiques, 2004, v:23, n:10, pp:1247-1267 [Journal]
    
12. Jean-Luc Beuchat, Masaaki Shirase, Tsuyoshi Takagi, Eiji Okamoto
    An Algorithm for the nt Pairing Calculation in Characteristic Three and its Hardware Implementation. [Citation Graph (0, 0)][DBLP]
    IEEE Symposium on Computer Arithmetic, 2007, pp:97-104 [Conf]
    
13. Jean-Luc Beuchat, Nicolas Brisebarre, Jérémie Detrey, Eiji Okamoto
    Arithmetic Operators for Pairing-Based Cryptography. [Citation Graph (0, 0)][DBLP]
    CHES, 2007, pp:239-255 [Conf]
    
14. Jean-Luc Beuchat, Takanori Miyoshi, Yoshihito Oyama, Eiji Okamoto
    Multiplication over F_p^m on FPGA: A Survey. [Citation Graph (0, 0)][DBLP]
    ARC, 2007, pp:214-225 [Conf]
    
15. Jean-Luc Beuchat, Nicolas Brisebarre, Masaaki Shirase, Tsuyoshi Takagi, Eiji Okamoto
    A Coprocessor for the Final Exponentiation of the eta _T Pairing in Characteristic Three. [Citation Graph (0, 0)][DBLP]
    WAIFI, 2007, pp:25-39 [Conf]
    
16. Jean-Luc Beuchat
    Further Comments on ``Residue-to-Binary Converters Based on New Chinese Remainder Theorems'' [Citation Graph (0, 0)][DBLP]
    CoRR, 2007, v:0, n:, pp:- [Journal]
    
17. 
    Multi-core Implementation of the Tate Pairing over Supersingular Elliptic Curves. [Citation Graph (, )][DBLP]
    
    
18. 
    Hardware Accelerator for the Tate Pairing in Characteristic Three Based on Karatsuba-Ofman Multipliers. [Citation Graph (, )][DBLP]
    
    
19. 
    A Comparison between Hardware Accelerators for the Modified Tate Pairing over F_2^m and F_3^m. [Citation Graph (, )][DBLP]