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João M. P. Cardoso: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. João M. P. Cardoso
    On Estimations for Compiling Software to FPGA-based Systems. [Citation Graph (0, 0)][DBLP]
    ASAP, 2005, pp:225-230 [Conf]
  2. João M. P. Cardoso
    Dynamic loop pipelining in data-driven architectures. [Citation Graph (0, 0)][DBLP]
    Conf. Computing Frontiers, 2005, pp:106-115 [Conf]
  3. João M. P. Cardoso, Markus Weinhardt
    From C Programs to the Configure-Execute Model. [Citation Graph (0, 0)][DBLP]
    DATE, 2003, pp:10576-10581 [Conf]
  4. Rui Rodrigues, João M. P. Cardoso
    An Infrastructure to Functionally Test Designs Generated by Compilers Targeting FPGAs. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:30-31 [Conf]
  5. João M. P. Cardoso, Horácio C. Neto
    Macro-Based Hardware Compilation of Java(tm) Bytecodes into a Dynamic Reconfigurable Computing System. [Citation Graph (0, 0)][DBLP]
    FCCM, 1999, pp:2-11 [Conf]
  6. João M. P. Cardoso, Markus Weinhardt
    Fast and Guaranteed C Compilation onto the PACT-XPP? Reconfigurable Computing Platform. [Citation Graph (0, 0)][DBLP]
    FCCM, 2002, pp:291-292 [Conf]
  7. João M. P. Cardoso, Horácio C. Neto
    Compilation Increasing the Scheduling Scope for Multi-memory-FPGA-Based Custom Computing Machines. [Citation Graph (0, 0)][DBLP]
    FPL, 2001, pp:523-533 [Conf]
  8. João M. P. Cardoso, Markus Weinhardt
    XPP-VC: A C Compiler with Temporal Partitioning for the PACT-XPP Architecture. [Citation Graph (0, 0)][DBLP]
    FPL, 2002, pp:864-874 [Conf]
  9. Ricardo Ferreira, João M. P. Cardoso, Horácio C. Neto
    An Environment for Exploring Data-Driven Architectures. [Citation Graph (0, 0)][DBLP]
    FPL, 2004, pp:1022-1026 [Conf]
  10. Vanderlei Bonato, Adriano K. Sanches, Márcio M. Fernandes, João M. P. Cardoso, Eduardo D. V. Simões, Eduardo Marques
    A Real Time Gesture Recognition System for Mobile Robots. [Citation Graph (0, 0)][DBLP]
    ICINCO (2), 2004, pp:207-214 [Conf]
  11. João M. P. Cardoso, Horácio C. Neto
    An Enhanced Static-List Scheduling Algorithm for Temporal Partitioning onto RPUs. [Citation Graph (0, 0)][DBLP]
    VLSI, 1999, pp:485-496 [Conf]
  12. João M. P. Cardoso
    Loop Dissevering: A Technique for Temporally Partitioning Loops in Dynamically Reconfigurable Computing Platforms. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2003, pp:181- [Conf]
  13. Ricardo Ferreira, Alisson Garcia, Tiago Teixeira, João M. P. Cardoso
    A Polynomial Placement Algorithm for Data Driven Coarse-Grained Reconfigurable Architectures. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2007, pp:61-66 [Conf]
  14. R. A. Gonçalves, P. A. Moraes, João M. P. Cardoso, D. F. Wolf, Márcio M. Fernandes, Roseli A. Francelin Romero, Eduardo Marques
    ARCHITECT-R: A System for Reconfigurable Robots Design. [Citation Graph (0, 0)][DBLP]
    SAC, 2003, pp:679-683 [Conf]
  15. João M. P. Cardoso
    Self-loop Pipelining and Reconfigurable Dataflow Arrays. [Citation Graph (0, 0)][DBLP]
    SAMOS, 2004, pp:234-243 [Conf]
  16. João M. P. Cardoso, Pedro C. Diniz
    Modeling Loop Unrolling: Approaches and Open Issues. [Citation Graph (0, 0)][DBLP]
    SAMOS, 2004, pp:224-233 [Conf]
  17. Ricardo Ferreira, João M. P. Cardoso, Andre Toledo, Horácio C. Neto
    Data-Driven Regular Reconfigurable Arrays: Design Space Exploration and Mapping. [Citation Graph (0, 0)][DBLP]
    SAMOS, 2005, pp:41-50 [Conf]
  18. João M. P. Cardoso, Horácio C. Neto
    Compilation for FPGA-Based Reconfigurable Hardware. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2003, v:20, n:2, pp:65-75 [Journal]
  19. João M. P. Cardoso
    On Combining Temporal Partitioning and Sharing of Functional Units in Compilation for Reconfigurable Architectures. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2003, v:52, n:10, pp:1362-1375 [Journal]
  20. Carlos Morra, João M. P. Cardoso, Jürgen Becker
    Using Rewriting Logic to Match Patterns of Instructions from a Compiler Intermediate Form to Coarse-Grained Processing Elements. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2007, pp:1-8 [Conf]
  21. João Bispo, Ioannis Sourdis, João M. P. Cardoso, Stamatis Vassiliadis
    Synthesis of Regular Expressions Targeting FPGAs: Current Status and Open Issues. [Citation Graph (0, 0)][DBLP]
    ARC, 2007, pp:179-190 [Conf]
  22. João M. P. Cardoso
    New challenges in computer science education. [Citation Graph (0, 0)][DBLP]
    ITiCSE, 2005, pp:203-207 [Conf]
  23. Rui Rodrigues, João M. P. Cardoso
    An Infrastructure to Functionally Test Designs Generated by Compilers Targeting FPGAs [Citation Graph (0, 0)][DBLP]
    CoRR, 2007, v:0, n:, pp:- [Journal]

  24. A Data-Driven Approach for Pipelining Sequences of Data-Dependent Loops. [Citation Graph (, )][DBLP]


  25. Combining Rewriting-Logic, Architecture Generation, and Simulation to Exploit Coarse-Grained Reconfigurable Architectures. [Citation Graph (, )][DBLP]


  26. Aggressive Loop Pipelining for Reconfigurable Architectures. [Citation Graph (, )][DBLP]


  27. Automatic generation of FPGA hardware accelerators using a domain specific language. [Citation Graph (, )][DBLP]


  28. Sorting Units for FPGA-Based Embedded Systems. [Citation Graph (, )][DBLP]


  29. Mobile Context Provider for Social Networking. [Citation Graph (, )][DBLP]


  30. The current feasibility of gesture recognition for a smartphone using J2ME. [Citation Graph (, )][DBLP]


  31. LALP: A Novel Language to Program Custom FPGA-Based Architectures. [Citation Graph (, )][DBLP]


  32. On Simplifying Placement and Routing by Extending Coarse-Grained Reconfigurable Arrays with Omega Networks. [Citation Graph (, )][DBLP]


  33. An FPGA Implementation for a Kalman Filter with Application to Mobile Robotics. [Citation Graph (, )][DBLP]


  34. On Adapting Power Estimation Models for Embedded Soft-Core Processors. [Citation Graph (, )][DBLP]


  35. Context Inference for Mobile Applications in the UPCASE Project. [Citation Graph (, )][DBLP]


  36. An Analysis of Navigation Algorithms for Smartphones Using J2ME. [Citation Graph (, )][DBLP]


  37. Retargeting, Evaluating, and Generating Reconfigurable Array-Based Architectures. [Citation Graph (, )][DBLP]


  38. Compiling for reconfigurable computing: A survey. [Citation Graph (, )][DBLP]


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