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Praveen K. Murthy:
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Publications of Author
- Shuvra S. Bhattacharyya, Praveen K. Murthy, Edward A. Lee
Optimized software synthesis for synchronous dataflow. [Citation Graph (0, 0)][DBLP] ASAP, 1997, pp:250-262 [Conf]
- Praveen K. Murthy, Etan G. Cohen, Steve Rowland
System canvas: a new design environment for embedded DSP and telecommunication systems. [Citation Graph (0, 0)][DBLP] CODES, 2001, pp:54-59 [Conf]
- Praveen K. Murthy, Shuvra S. Bhattacharyya
Shared Memory Implementations of Synchronous Dataflow Specifications. [Citation Graph (0, 0)][DBLP] DATE, 2000, pp:404-410 [Conf]
- Praveen K. Murthy, Shuvra S. Bhattacharyya
A Buffer Merging Technique for Reducing Memory Requirements of Synchronous Dataflow Specifications. [Citation Graph (0, 0)][DBLP] ISSS, 1999, pp:78-84 [Conf]
- Ming-Yung Ko, Praveen K. Murthy, Shuvra S. Bhattacharyya
Compact Procedural Implementation in DSP Software Synthesis Through Recursive Graph Decomposition. [Citation Graph (0, 0)][DBLP] SCOPES, 2004, pp:47-61 [Conf]
- Felice Balarin, Luciano Lavagno, Praveen K. Murthy, Alberto L. Sangiovanni-Vincentelli
Scheduling for Embedded Real-Time Systems. [Citation Graph (0, 0)][DBLP] IEEE Design & Test of Computers, 1998, v:15, n:1, pp:71-82 [Journal]
- Praveen K. Murthy, Shuvra S. Bhattacharyya, Edward A. Lee
Joint Minimization of Code and Data for Synchronous Dataflow Programs. [Citation Graph (0, 0)][DBLP] Formal Methods in System Design, 1997, v:11, n:1, pp:41-70 [Journal]
- Praveen K. Murthy, Shuvra S. Bhattacharyya
Shared buffer implementations of signal processing systems usinglifetime analysis techniques. [Citation Graph (0, 0)][DBLP] IEEE Trans. on CAD of Integrated Circuits and Systems, 2001, v:20, n:2, pp:177-198 [Journal]
- Praveen K. Murthy, Shuvra S. Bhattacharyya
Buffer merging - a powerful technique for reducing memory requirements of synchronous dataflow specifications. [Citation Graph (0, 0)][DBLP] ACM Trans. Design Autom. Electr. Syst., 2004, v:9, n:2, pp:212-237 [Journal]
- Ming-Yung Ko, Praveen K. Murthy, Shuvra S. Bhattacharyya
Beyond single-appearance schedules: Efficient DSP software synthesis using nested procedure calls. [Citation Graph (0, 0)][DBLP] ACM Trans. Embedded Comput. Syst., 2007, v:6, n:2, pp:- [Journal]
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