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Walter Anheier: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Ansgar Drolshagen, H. Henkelmann, Walter Anheier
    Processor Elements for the Standard Cell Implementation of Residue Number Systems. [Citation Graph (0, 0)][DBLP]
    ASAP, 1997, pp:116-123 [Conf]
  2. Ajoy Kumar Palit, Lei Wu, Kishore K. Duganapalli, Walter Anheier, Jürgen Schlöffel
    A New, Flexible and Very Accurate Crosstalk Fault Model to Analyze the Effects of Coupling Noise between the Interconnects on Signal Integrity Losses in Deep Submicron Chips. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2005, pp:22-27 [Conf]
  3. B. Lauerbach, Walter Anheier
    Segmentierung farbiger kartographischer Vorlagen in empfindungsgemäßen Farbräumen. [Citation Graph (0, 0)][DBLP]
    DAGM-Symposium, 1993, pp:733-740 [Conf]
  4. Ajoy Kumar Palit, Kishore K. Duganapalli, Walter Anheier
    XSIM: An Efficient Crosstalk Simulator for Analysis and Modeling of Signal Integrity Faults in Both Defective and Defect-free Interconnects. [Citation Graph (0, 0)][DBLP]
    DDECS, 2007, pp:161-164 [Conf]
  5. Ajoy Kumar Palit, Volker Meyer, Walter Anheier, Jürgen Schlöffel
    Modeling and Analysis of Crosstalk Coupling Effect on the Victim Interconnect Using the ABCD Network Model. [Citation Graph (0, 0)][DBLP]
    DFT, 2004, pp:174-182 [Conf]
  6. Ajoy Kumar Palit, Kishore K. Duganapalli, Walter Anheier
    Influence of Resistive Bridging Fault on Crosstalk Coupling Effects in On-Chip Aggressor-Victim Interconnects. [Citation Graph (0, 0)][DBLP]
    DFT, 2006, pp:336-344 [Conf]
  7. Stefan Radtke, Jens Bargfrede, Walter Anheier
    Distributed automatic test pattern generation with a parallel FAN algorithm. [Citation Graph (0, 0)][DBLP]
    ICCD, 1995, pp:698-0 [Conf]
  8. Beom-Ik Cheon, Walter Anheier, Rainer Laur
    A New Strategy for Test Pattern Generation in Sequential Circuits. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1994, pp:77-80 [Conf]
  9. Ajoy Kumar Palit, Kishore K. Duganapalli, Walter Anheier
    Modeling of Crosstalk Fault in Defective Interconnects. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2006, pp:340-349 [Conf]
  10. Ansgar Drolshagen, Walter Anheier, C. Chandra Sekhar
    A Residue Number Arithmetic based Circuit for Pipelined Computation of Autocorrelation Coefficients of Speech Signal. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1998, pp:122-127 [Conf]
  11. Ajoy Kumar Palit, Volker Meyer, Walter Anheier, Jürgen Schlöffel
    ABCD Modeling of Crosstalk Coupling Noise to Analyze the Signal Integrity Losses on the Victim Interconnect in DSM Chips. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2005, pp:354-359 [Conf]

  12. Timing Arc based logic analysis for false noise reduction. [Citation Graph (, )][DBLP]


  13. Reduction of Crosstalk Pessimism using Tendency Graph Approach. [Citation Graph (, )][DBLP]


  14. Adaptive Branch and Bound Using SAT to Estimate False Crosstalk. [Citation Graph (, )][DBLP]


  15. Test Pattern Generation and Compaction for Crosstalk Induced Glitches and Delay Faults. [Citation Graph (, )][DBLP]


  16. Segmentation of Scanned Maps in Uniform Color Spaces. [Citation Graph (, )][DBLP]


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