Search the dblp DataBase

Publications of Author

1. Andy Lambrechts, Praveen Raghavan, Anthony Leroy, Guillermo Talavera, Tom Vander Aa, Murali Jayapala, Francky Catthoor, Diederik Verkest, Geert Deconinck, Henk Corporaal, Frédéric Robert, Jordi Carrabina
   Power Breakdown Analysis for a Heterogeneous NoC Platform Running a Video Application. [Citation Graph (0, 0)][DBLP]
   ASAP, 2005, pp:179-184 [Conf]
   
2. Antoni Portero, Guillermo Talavera, Marius Monton, Borja Martínez, Francky Catthoor, Jordi Carrabina
   Dynamic Voltage Scaling for Power Efficient MPEG4-SP Implementation. [Citation Graph (0, 0)][DBLP]
   ASAP, 2006, pp:257-260 [Conf]
   
3. Lluis Ribas, Jordi Carrabina
   Analysis of Switch-Level Faults by Symbolic Simulation. [Citation Graph (0, 0)][DBLP]
   DAC, 1995, pp:352-357 [Conf]
   
4. Lluis Ribas, Jordi Carrabina
   On the Reuse of Symbolic Simulation Results for Incremental Equivalence Verification of Switch-Level Circuits. [Citation Graph (0, 0)][DBLP]
   DATE, 1998, pp:624-0 [Conf]
   
5. Lluis Ribas, Jordi Carrabina
   Digital MOS Circuit Partitioning with Symbolic Modeling. [Citation Graph (0, 0)][DBLP]
   DATE, 1999, pp:503-508 [Conf]
   
6. Francis Calmon, M. Fathallah, P. J. Viverge, Christian Gontrand, Jordi Carrabina, P. Foussier
   FPGA and Mixed FPGA-DSP Implementations of Electrical Drive Algorithms. [Citation Graph (0, 0)][DBLP]
   FPL, 2002, pp:1144-1147 [Conf]
   
7. Ferran Lisa, Faustino Cuadrado, Dolores Rexachs, Jordi Carrabina
   A reconfigurable coprocessor for a PCI-based real time computer vision system. [Citation Graph (0, 0)][DBLP]
   FPL, 1997, pp:392-399 [Conf]
   
8. R. Peset Llopis, Lluis Ribas, Jordi Carrabina
   Short Destabilizing Paths in Timing Verification. [Citation Graph (0, 0)][DBLP]
   ICCD, 1994, pp:160-163 [Conf]
   
9. Lluis Ribas, Jordi Carrabina
   Symbolic Analysis for Fault Detection in Switch-Level Circuits. [Citation Graph (0, 0)][DBLP]
   ISCAS, 1995, pp:1235-1238 [Conf]
   
10. Jordi Carrabina, Ferran Lisa, Narcís Avellana, Conrado J. Pérez Vicente, Elena Valderrama
    VLSI Fully Connected Neural Networks for the Implementation of other Topologies. [Citation Graph (0, 0)][DBLP]
    IWANN, 1991, pp:277-284 [Conf]
    
11. Jordi Carrabina, Ferran Lisa, Vicens Gaitan, Lluís Garrido, Elena Valderrama
    Hardware Implementation of a Neural Network for High Energy Physics Application. [Citation Graph (0, 0)][DBLP]
    IWANN, 1993, pp:426-431 [Conf]
    
12. Ferran Lisa, Jordi Carrabina, Conrado J. Pérez Vicente, Narcís Avellana, Elena Valderrama
    Feed Forward Network for Vehicle License Character Recognition. [Citation Graph (0, 0)][DBLP]
    IWANN, 1993, pp:638-644 [Conf]
    
13. Conrado J. Pérez Vicente, Jordi Carrabina, F. Garrido, Elena Valderrama
    Learning Algorithm for Feed-Forward Neural Networks with Discrete Synapses. [Citation Graph (0, 0)][DBLP]
    IWANN, 1991, pp:144-152 [Conf]
    
14. Francisco-Javier Veredas, Jordi Carrabina
    Power Dissipation Impact of the Technology Mapping Synthesis on Look-Up Table Architectures. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2005, pp:666-673 [Conf]
    
15. Ferran Lisa-Mingo, Jordi Carrabina
    A Library of Memory Controllers for an Image Processing Prototyping System. [Citation Graph (0, 0)][DBLP]
    International Workshop on Rapid System Prototyping, 1998, pp:188-193 [Conf]
    
16. Moisès Serra, Pere Martí, Jordi Carrabina
    Implementation of a Channel Equalizer for OFDM Wireless LANs. [Citation Graph (0, 0)][DBLP]
    IEEE International Workshop on Rapid System Prototyping, 2004, pp:232-238 [Conf]
    
17. Conrado J. Pérez Vicente, Jordi Carrabina, Elena Valderrama
    Discrete Learning in Feed-Forward Neural Networks. [Citation Graph (0, 0)][DBLP]
    Int. J. Neural Syst., 1991, v:2, n:4, pp:323-329 [Journal]
    
18. Jordi Riera, Lluis Ribas, A. Josep Velasco, Jordi Carrabina
    Deriving cost functions from cell libraries and real ICs to allow real area-power-delay trade-off in early stages of logic synthesis. [Citation Graph (0, 0)][DBLP]
    Journal of Systems Architecture, 1997, v:43, n:1-5, pp:119-122 [Journal]
    
19. José Luis Merino, Lluís Teres, Jordi Carrabina
    A current copying structure for current-mode monotonic digital-to-analog converters. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]
    
20. 
    Jumble: A Hardware-in-the-Loop Simulation System for JHDL. [Citation Graph (, )][DBLP]
    
    
21. 
    Developing Ontologies for Legal Multimedia Applications. [Citation Graph (, )][DBLP]
    
    
22. 
    The e-Sentencias Prototype: A Procedural Ontology for Legal Multimedia Applications in the Spanish Civil Courts. [Citation Graph (, )][DBLP]
    
    
23. 
    xENoC - An eXperimental Network-On-Chip Environment for Parallel Distributed Computing on NoC-based MPSoC Architectures. [Citation Graph (, )][DBLP]
    
    
24. 
    Legal Knowledge Acquisition and Multimedia Applications. [Citation Graph (, )][DBLP]
    
    
25. 
    Front-End ADC Requirements for Uniform Bandpass Sampling in SDR. [Citation Graph (, )][DBLP]
    
    
26. 
    Hardware Synthesis of Parallel Machines from SystemC. [Citation Graph (, )][DBLP]
    
    
27. 
    Adding Tags to Courses to Improve Evaluation - A Multiplatform LCMS Approach that Allows Multidimensional Analysis. [Citation Graph (, )][DBLP]