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Sanjay V. Rajopadhye: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Scott Bowden, Doran Wilde, Sanjay V. Rajopadhye
    Quadratic Control Signals in Linear Systolic Arrays. [Citation Graph (0, 0)][DBLP]
    ASAP, 2000, pp:268-275 [Conf]
  2. DaeGon Kim, Sanjay V. Rajopadhye
    An Improved Systolic Architecture for LU Decomposition. [Citation Graph (0, 0)][DBLP]
    ASAP, 2006, pp:231-238 [Conf]
  3. Lakshminarayanan Renganarayanan, Sanjay V. Rajopadhye
    Switched Memory Architectures-Moving Beyond Systolic Arrays. [Citation Graph (0, 0)][DBLP]
    ASAP, 2003, pp:28-39 [Conf]
  4. Patrick M. Lenders, Sanjay V. Rajopadhye
    Synthesis of Multirate VLSI Arrays. [Citation Graph (0, 0)][DBLP]
    ASAP, 1995, pp:310-321 [Conf]
  5. Patrice Quinton, Sanjay V. Rajopadhye, Tanguy Risset
    Extension Of The Alpha Language To Recurrences On Sparse Periodic Domains. [Citation Graph (0, 0)][DBLP]
    ASAP, 1996, pp:391-401 [Conf]
  6. Doran Wilde, Sanjay V. Rajopadhye
    The naive execution of affine recurrence equations. [Citation Graph (0, 0)][DBLP]
    ASAP, 1995, pp:1-12 [Conf]
  7. Sanjay V. Rajopadhye
    An improved systolic algorithm for the algebraic path problem. [Citation Graph (0, 0)][DBLP]
    Algorithms and Parallel VLSI Architectures, 1991, pp:187-198 [Conf]
  8. Rumen Andonov, Sanjay V. Rajopadhye
    Optimal Tile Sizing. [Citation Graph (0, 0)][DBLP]
    CONPAR, 1994, pp:701-712 [Conf]
  9. Sanjay V. Rajopadhye, Kolin Paul
    A 1.5-D Architecture for Back-Propagation Training. [Citation Graph (0, 0)][DBLP]
    ERSA, 2005, pp:112-118 [Conf]
  10. Rumen Andonov, Sanjay V. Rajopadhye, Nicola Yanev
    Optimal Orthogonal Tiling. [Citation Graph (0, 0)][DBLP]
    Euro-Par, 1998, pp:480-490 [Conf]
  11. Sanjay V. Rajopadhye, Claude Tadonki, Tanguy Risset
    The Algebraic Path Problem Revisited. [Citation Graph (0, 0)][DBLP]
    Euro-Par, 1999, pp:698-707 [Conf]
  12. Doran Wilde, Sanjay V. Rajopadhye
    Memory Reuse Analysis in the Polyhedral Model. [Citation Graph (0, 0)][DBLP]
    Euro-Par, Vol. I, 1996, pp:389-397 [Conf]
  13. Steven Derrien, Sanjay V. Rajopadhye
    FCCMS and the Memory Wall. [Citation Graph (0, 0)][DBLP]
    FCCM, 2000, pp:329-330 [Conf]
  14. Patrice Quinton, Sanjay V. Rajopadhye, Doran Wilde
    Deriving Imperative Code from Functional Programs. [Citation Graph (0, 0)][DBLP]
    FPCA, 1995, pp:36-44 [Conf]
  15. Steven Derrien, Sanjay V. Rajopadhye
    Loop Tiling for Reconfigurable Accelerators. [Citation Graph (0, 0)][DBLP]
    FPL, 2001, pp:398-408 [Conf]
  16. Sanjay V. Rajopadhye, S. Purushothaman, Richard Fujimoto
    On Synthesizing Systolic Arrays from Recurrence Equations with Linear Dependencies. [Citation Graph (0, 0)][DBLP]
    FSTTCS, 1986, pp:488-503 [Conf]
  17. Virginia Mary Lo, Sanjay V. Rajopadhye, Samik Gupta, David Keldsen, Moataz A. Mohamed, Jan Arne Telle
    OREGAMI: Software Tools for Mapping Parallel Computations to Parallel Architectures. [Citation Graph (0, 0)][DBLP]
    ICPP (2), 1990, pp:88-92 [Conf]
  18. Virginia Mary Lo, Sanjay V. Rajopadhye, Samik Gupta, David Keldsen, Moataz A. Mohamed, Jan Arne Telle
    Mapping Divide-and-Conquer Algorithms to Parallel Architectures. [Citation Graph (0, 0)][DBLP]
    ICPP (3), 1990, pp:128-135 [Conf]
  19. Manju Manjunathaiah, Graham M. Megson, Sanjay V. Rajopadhye, Tanguy Risset
    Uniformization of Affine Dependance Programs for Parallel Embedded System Design. [Citation Graph (0, 0)][DBLP]
    ICPP, 2001, pp:205-213 [Conf]
  20. Sanjay V. Rajopadhye, Prakash Panangaden
    Verification of Systolic Arrays: A Stream Function Approach. [Citation Graph (0, 0)][DBLP]
    ICPP, 1986, pp:773-775 [Conf]
  21. Björn Lisper, Sanjay V. Rajopadhye
    Reasoning about Permutations in Regular Arrays. [Citation Graph (0, 0)][DBLP]
    Designing Correct Circuits, 1992, pp:139-157 [Conf]
  22. David Cachera, Patrice Quinton, Sanjay V. Rajopadhye, Tanguy Risset
    Proving Properties of Multidimensional Recurrences with Application to Regular Parallel Algorithms. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2001, pp:148- [Conf]
  23. Patrice Quinton, Sanjay V. Rajopadhye, Doran Wilde
    On deriving data parallel code from a functional program. [Citation Graph (0, 0)][DBLP]
    IPPS, 1995, pp:766-0 [Conf]
  24. Xiaoxiong Zhong, Sanjay V. Rajopadhye, Virginia Mary Lo
    Parallel Implementation of Divide-and-Conquer Algorithms on Binary de Bruijn Networks. [Citation Graph (0, 0)][DBLP]
    IPPS, 1992, pp:103-107 [Conf]
  25. Florent de Dinechin, Doran Wilde, Sanjay V. Rajopadhye, Rumen Andonov
    A Regular VLSI Array for an Irregular Algorithm. [Citation Graph (0, 0)][DBLP]
    IRREGULAR, 1996, pp:195-200 [Conf]
  26. Steven Derrien, Sanjay V. Rajopadhye, Susmita Sur-Kolay
    Combined instruction and loop parallelism in array synthesis for FPGAs. [Citation Graph (0, 0)][DBLP]
    ISSS, 2001, pp:165-170 [Conf]
  27. Sanjay V. Rajopadhye, Steven Derrien
    Energy/Power Estimation of Regular Processor Arrays. [Citation Graph (0, 0)][DBLP]
    ISSS, 2002, pp:50-55 [Conf]
  28. Lakshminarayanan Renganarayanan, U. Ramakrishna, Sanjay V. Rajopadhye
    Combined ILP and Register Tiling: Analytical Model and Optimization Framework. [Citation Graph (0, 0)][DBLP]
    LCPC, 2005, pp:244-258 [Conf]
  29. Steven Derrien, Sanjay V. Rajopadhye, Susmita Sur-Kolay
    Optimal Partitioning for FPGA Based Regular Array Implementations. [Citation Graph (0, 0)][DBLP]
    PARELEC, 2000, pp:155-159 [Conf]
  30. Sanjay V. Rajopadhye, Richard Fujimoto
    Systolic Array Synthesis by Static Analysis of Program Dependencies. [Citation Graph (0, 0)][DBLP]
    PARLE (1), 1987, pp:295-310 [Conf]
  31. Xiaoxiong Zhong, Sanjay V. Rajopadhye
    Deriving Fully Efficient Systolic Arrays by Quasi-Linear Allocation Functions. [Citation Graph (0, 0)][DBLP]
    PARLE (1), 1991, pp:219-236 [Conf]
  32. Gautam Gupta, Sanjay V. Rajopadhye
    Simplifying reductions. [Citation Graph (0, 0)][DBLP]
    POPL, 2006, pp:30-41 [Conf]
  33. Gautam Gupta, Sanjay V. Rajopadhye
    The Z-polyhedral model. [Citation Graph (0, 0)][DBLP]
    PPOPP, 2007, pp:237-248 [Conf]
  34. Sanjay V. Rajopadhye, Manjunath Muddarangegowda
    Parallel Assignment, Reduction and Communication for Data Parallel Programming. [Citation Graph (0, 0)][DBLP]
    PPSC, 1993, pp:850-853 [Conf]
  35. Lakshminarayanan Renganarayanan, Sanjay V. Rajopadhye
    A Geometric Programming Framework for Optimal Multi-Level Tiling. [Citation Graph (0, 0)][DBLP]
    SC, 2004, pp:18- [Conf]
  36. Stephan Balev, Patrice Quinton, Sanjay V. Rajopadhye, Tanguy Risset
    Linear Programming Models for Scheduling Systems of Affine Recurrence Equations - A Comparative Study. [Citation Graph (0, 0)][DBLP]
    SPAA, 1998, pp:250-258 [Conf]
  37. Rumen Andonov, Stephan Balev, Sanjay V. Rajopadhye, Nicola Yanev
    Optimal semi-oblique tiling. [Citation Graph (0, 0)][DBLP]
    SPAA, 2001, pp:153-162 [Conf]
  38. Gautam Gupta, Sanjay V. Rajopadhye, Patrice Quinton
    Scheduling reductions on realistic machines. [Citation Graph (0, 0)][DBLP]
    SPAA, 2002, pp:117-126 [Conf]
  39. Sanjay V. Rajopadhye
    Analysis of Affine Communication Specifications. [Citation Graph (0, 0)][DBLP]
    SPDP, 1993, pp:530-537 [Conf]
  40. Sanjay V. Rajopadhye
    Synthesizing Systolic Arrays with Control Signals from Recurrence Equations. [Citation Graph (0, 0)][DBLP]
    Distributed Computing, 1989, v:3, n:2, pp:88-105 [Journal]
  41. Fabien Quilleré, Sanjay V. Rajopadhye, Doran Wilde
    Generation of Efficient Nested Loops from Polyhedra. [Citation Graph (0, 0)][DBLP]
    International Journal of Parallel Programming, 2000, v:28, n:5, pp:469-498 [Journal]
  42. Rumen Andonov, Sanjay V. Rajopadhye
    Optimal Orthogonal Tiling of 2-D Iterations. [Citation Graph (0, 0)][DBLP]
    J. Parallel Distrib. Comput., 1997, v:45, n:2, pp:159-165 [Journal]
  43. Clémentin Tayou Djamégni, Patrice Quinton, Sanjay V. Rajopadhye, Tanguy Risset
    Derivation of systolic algorithms for the algebraic path problem by recurrence transformations. [Citation Graph (0, 0)][DBLP]
    Parallel Computing, 2000, v:26, n:11, pp:1429-1445 [Journal]
  44. Sanjay V. Rajopadhye, Richard Fujimoto
    Synthesizing systolic arrays from recurrence equations. [Citation Graph (0, 0)][DBLP]
    Parallel Computing, 1990, v:14, n:2, pp:163-189 [Journal]
  45. Rumen Andonov, Patrice Quinton, Sanjay V. Rajopadhye, Doran Wilde
    A Shift Registered-Based Systolic Array for the Unbounded Knapsack Problem. [Citation Graph (0, 0)][DBLP]
    Parallel Processing Letters, 1995, v:5, n:, pp:251-262 [Journal]
  46. Patrice Quinton, Sanjay V. Rajopadhye, Tanguy Risset
    On Manipulating Z-Polyhedra Using a Canonical Representation. [Citation Graph (0, 0)][DBLP]
    Parallel Processing Letters, 1997, v:7, n:2, pp:181-194 [Journal]
  47. Doran Wilde, Sanjay V. Rajopadhye
    Memory Reuse Analysis in the Polyhedral Model. [Citation Graph (0, 0)][DBLP]
    Parallel Processing Letters, 1997, v:7, n:2, pp:203-215 [Journal]
  48. Patrick M. Lenders, Sanjay V. Rajopadhye
    Multirate VLSI Arrays and Their Synthesis. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1997, v:46, n:5, pp:515-529 [Journal]
  49. Fabien Quilleré, Sanjay V. Rajopadhye
    Optimizing memory usage in the polyhedral model. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Program. Lang. Syst., 2000, v:22, n:5, pp:773-815 [Journal]
  50. Rumen Andonov, Stephan Balev, Sanjay V. Rajopadhye, Nicola Yanev
    Optimal Semi-Oblique Tiling. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Parallel Distrib. Syst., 2003, v:14, n:9, pp:944-960 [Journal]
  51. Rumen Andonov, Sanjay V. Rajopadhye
    Knapsack on VLSI: from Algorithm to Optimal Circuit. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Parallel Distrib. Syst., 1997, v:8, n:6, pp:545-561 [Journal]
  52. Virginia Mary Lo, Sanjay V. Rajopadhye, Jan Arne Telle, Xiaoxiong Zhong
    Parallel Divide and Conquer on Meshes. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Parallel Distrib. Syst., 1996, v:7, n:10, pp:1049-1058 [Journal]
  53. Lakshminarayanan Renganarayanan, Manjukumar Harthikote-Matha, Rinku Dewri, Sanjay V. Rajopadhye
    Towards Optimal Multi-level Tiling for Stencil Computations. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2007, pp:1-10 [Conf]
  54. Gautam Gupta, DaeGon Kim, Sanjay V. Rajopadhye
    Scheduling in the Z-Polyhedral Model. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2007, pp:1-10 [Conf]
  55. DaeGon Kim, Gautam, Sanjay V. Rajopadhye
    On Control Signals for Multi-Dimensional Time. [Citation Graph (0, 0)][DBLP]
    LCPC, 2006, pp:141-155 [Conf]
  56. Lakshminarayanan Renganarayanan, DaeGon Kim, Sanjay V. Rajopadhye, Michelle Mills Strout
    Parameterized tiled loops for free. [Citation Graph (0, 0)][DBLP]
    PLDI, 2007, pp:405-414 [Conf]

  57. Automatic creation of tile size selection models. [Citation Graph (, )][DBLP]


  58. Smashing: Folding Space to Tile through Time. [Citation Graph (, )][DBLP]


  59. Efficient Tiled Loop Generation: D-Tiling. [Citation Graph (, )][DBLP]


  60. A domain specific interconnect for reconfigurable computing. [Citation Graph (, )][DBLP]


  61. Pure Systolic Array for a Class of Dynamic Dependency Recurrences. [Citation Graph (, )][DBLP]


  62. Multi-level tiling: M for the price of one. [Citation Graph (, )][DBLP]


  63. Positivity, posynomials and tile size selection. [Citation Graph (, )][DBLP]


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