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Samarjit Chakraborty: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Samarjit Chakraborty
    Towards a Framework for System-Level Design of Multiprocessor SoC Platforms for Media Processing. [Citation Graph (0, 0)][DBLP]
    ASAP, 2005, pp:65-72 [Conf]
  2. Alexander Maxiaguine, Simon Künzli, Samarjit Chakraborty, Lothar Thiele
    Rate analysis for streaming applications with on-chip buffer constraints. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:131-136 [Conf]
  3. Alexander Maxiaguine, Samarjit Chakraborty, Lothar Thiele
    DVS for buffer-constrained architectures with predictable QoS-energy tradeoffs. [Citation Graph (0, 0)][DBLP]
    CODES+ISSS, 2005, pp:111-116 [Conf]
  4. Alexander Maxiaguine, Yongxin Zhu, Samarjit Chakraborty, Weng-Fai Wong
    Tuning SoC platforms for multimedia processing: identifying limits and tradeoffs. [Citation Graph (0, 0)][DBLP]
    CODES+ISSS, 2004, pp:128-133 [Conf]
  5. Balaji Raman, Samarjit Chakraborty
    Application-specific workload shaping in multimedia-enabled personal mobile devices. [Citation Graph (0, 0)][DBLP]
    CODES+ISSS, 2006, pp:4-9 [Conf]
  6. Samarjit Chakraborty, Thomas Erlebach, Simon Künzli, Lothar Thiele
    Schedulability of event-driven code blocks in real-time embedded systems. [Citation Graph (0, 0)][DBLP]
    DAC, 2002, pp:616-621 [Conf]
  7. Yan Gu, Samarjit Chakraborty, Wei Tsang Ooi
    Games are up for DVFS. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:598-603 [Conf]
  8. Yanhong Liu, Samarjit Chakraborty, Wei Tsang Ooi
    Approximate VCCs: a new characterization of multimedia workloads for system-level MpSoC design. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:248-253 [Conf]
  9. Lothar Thiele, Samarjit Chakraborty, Matthias Gries, Simon Künzli
    A framework for evaluating design tradeoffs in packet processing architectures. [Citation Graph (0, 0)][DBLP]
    DAC, 2002, pp:880-885 [Conf]
  10. Samarjit Chakraborty, Simon Künzli, Lothar Thiele
    A General Framework for Analysing System Properties in Platform-Based Embedded System Designs. [Citation Graph (0, 0)][DBLP]
    DATE, 2003, pp:10190-10195 [Conf]
  11. Samarjit Chakraborty, Lothar Thiele
    A New Task Model for Streaming Applications and Its Schedulability Analysis. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:486-491 [Conf]
  12. Lothar Thiele, Samarjit Chakraborty, Matthias Gries, Alexander Maxiaguine, Jonas Greutert
    Embedded Software in Network Processors - Models and Algorithms. [Citation Graph (0, 0)][DBLP]
    EMSOFT, 2001, pp:416-434 [Conf]
  13. Christoph Ambühl, Samarjit Chakraborty, Bernd Gärtner
    Computing Largest Common Point Sets under Approximate Congruence. [Citation Graph (0, 0)][DBLP]
    ESA, 2000, pp:52-63 [Conf]
  14. Samarjit Chakraborty, Ye Wang, Wendong Huang
    A Perception-Aware Low-Power Software Audio Decoder for Portable Devices. [Citation Graph (0, 0)][DBLP]
    ESTImedia, 2005, pp:13-18 [Conf]
  15. Yanhong Liu, Samarjit Chakraborty, Wei Tsang Ooi, Ashish Gupta, Subramanian Mohan
    Workload Characterization and Cost-Quality Tradeoffs in MPEG-4 Decoding on Resource-Constrained Devices. [Citation Graph (0, 0)][DBLP]
    ESTImedia, 2005, pp:129-134 [Conf]
  16. Alexander Maxiaguine, Samarjit Chakraborty, Wei Tsang Ooi
    Identifying "representative" workloads in designing MpSoC platforms for media processing. [Citation Graph (0, 0)][DBLP]
    ESTImedia, 2004, pp:41-46 [Conf]
  17. Samarjit Chakraborty, Sudipta Dey, Kalyanmoy Deb
    Model-Based Object Recognition from a Complex Binary Imagery Using Genetic Algorithm. [Citation Graph (0, 0)][DBLP]
    EvoWorkshops, 1999, pp:150-161 [Conf]
  18. Sanjoy K. Baruah, Samarjit Chakraborty
    Schedulability analysis of non-preemptive recurring real-time tasks. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2006, pp:- [Conf]
  19. Yicheng Huang, Samarjit Chakraborty, Ye Wang
    Using offline bitstream analysis for power-aware video decoding in portable devices. [Citation Graph (0, 0)][DBLP]
    ACM Multimedia, 2005, pp:299-302 [Conf]
  20. Wendong Huang, Ye Wang, Samarjit Chakraborty
    Power-aware bandwidth and stereo-image scalable audio decoding. [Citation Graph (0, 0)][DBLP]
    ACM Multimedia, 2005, pp:291-294 [Conf]
  21. Balaji Raman, Samarjit Chakraborty, Wei Tsang Ooi
    Meeting CPU constraints by delaying playout of multimedia tasks. [Citation Graph (0, 0)][DBLP]
    NOSSDAV, 2005, pp:165-170 [Conf]
  22. Samarjit Chakraborty, Kalyanmoy Deb
    Analytic Curve Detection from a Noisy Binary Edge Map Using Genetic Algorithm. [Citation Graph (0, 0)][DBLP]
    PPSN, 1998, pp:129-138 [Conf]
  23. Samarjit Chakraborty, Matthias Gries, Lothar Thiele
    Supporting a Low Delay Best-Effort Class in the Presence of Real-Time Traffic. [Citation Graph (0, 0)][DBLP]
    IEEE Real Time Technology and Applications Symposium, 2002, pp:45-54 [Conf]
  24. Unmesh D. Bordoloi, Samarjit Chakraborty
    Interactive Schedulability Analysis. [Citation Graph (0, 0)][DBLP]
    IEEE Real Time Technology and Applications Symposium, 2006, pp:147-156 [Conf]
  25. Yanhong Liu, Samarjit Chakraborty, Radu Marculescu
    Generalized Rate Analysis for Media-Processing Platforms. [Citation Graph (0, 0)][DBLP]
    RTCSA, 2006, pp:305-314 [Conf]
  26. Shanmuga Priya Marimuthu, Samarjit Chakraborty
    A Framework for Compositional and Hierarchical Real-Time Scheduling. [Citation Graph (0, 0)][DBLP]
    RTCSA, 2006, pp:91-96 [Conf]
  27. Samarjit Chakraborty, Simon Künzli, Lothar Thiele
    Approximate Schedulability Analysis. [Citation Graph (0, 0)][DBLP]
    IEEE Real-Time Systems Symposium, 2002, pp:159-168 [Conf]
  28. Samarjit Chakraborty, Linh T. X. Phan, P. S. Thiagarajan
    Event Count Automata: A State-Based Model for Stream Processing Systems. [Citation Graph (0, 0)][DBLP]
    RTSS, 2005, pp:87-98 [Conf]
  29. Yanhong Liu, Alexander Maxiaguine, Samarjit Chakraborty, Wei Tsang Ooi
    Processor Frequency Selection for SoC Platforms for Multimedia Applications. [Citation Graph (0, 0)][DBLP]
    RTSS, 2004, pp:336-345 [Conf]
  30. Samarjit Chakraborty, Yanhong Liu, Nikolay Stoimenov, Lothar Thiele, Ernesto Wandeler
    Interface-Based Rate Analysis of Embedded Systems. [Citation Graph (0, 0)][DBLP]
    RTSS, 2006, pp:25-34 [Conf]
  31. Samarjit Chakraborty, Abhik Roychoudhury
    Tutorial T8B: Performance Debugging of Complex Embedded Systems. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2007, pp:13- [Conf]
  32. Samarjit Chakraborty, Somenath Biswas
    Approximation Algorithms for 3-D Commom Substructure Identification in Drug and Protein Molecules. [Citation Graph (0, 0)][DBLP]
    WADS, 1999, pp:253-264 [Conf]
  33. Samarjit Chakraborty, Thomas Erlebach, Lothar Thiele
    On the Complexity of Scheduling Conditional Real-Time Code. [Citation Graph (0, 0)][DBLP]
    WADS, 2001, pp:38-49 [Conf]
  34. Samarjit Chakraborty, Simon Künzli, Lothar Thiele, Andreas Herkersdorf, Patricia Sagmeister
    Performance evaluation of network processor architectures: combining simulation with analytical estimation. [Citation Graph (0, 0)][DBLP]
    Computer Networks, 2003, v:41, n:5, pp:641-665 [Journal]
  35. Alexander Maxiaguine, Samarjit Chakraborty, Simon Künzli, Lothar Thiele
    Evaluating Schedulers for Multimedia Processing on Buffer-Constrained SoC Platforms. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2004, v:21, n:5, pp:368-377 [Journal]
  36. Matthias Anlauff, Samarjit Chakraborty, Philipp W. Kutter, Alfonso Pierantonio, Lothar Thiele
    Generating an action notation environment from Montages descriptions. [Citation Graph (0, 0)][DBLP]
    STTT, 2001, v:3, n:4, pp:431-455 [Journal]
  37. Andrei Hagiescu, Unmesh D. Bordoloi, Samarjit Chakraborty, Prahladavaradan Sampath, P. Vignesh V. Ganesan, S. Ramesh
    Performance Analysis of FlexRay-based ECU Networks. [Citation Graph (0, 0)][DBLP]
    DAC, 2007, pp:284-289 [Conf]
  38. Balaji Raman, Samarjit Chakraborty, Wei Tsang Ooi, Santanu Dutta
    Reducing Data-Memory Footprint of Multimedia Applications by Delay Redistribution. [Citation Graph (0, 0)][DBLP]
    DAC, 2007, pp:738-743 [Conf]
  39. Lei Ju, Samarjit Chakraborty, Abhik Roychoudhury
    Accounting for cache-related preemption delay in dynamic priority schedulability analysis. [Citation Graph (0, 0)][DBLP]
    DATE, 2007, pp:1623-1628 [Conf]
  40. Samarjit Chakraborty
    Flexible modelling and performance debugging of real-time embedded multimedia systems. [Citation Graph (0, 0)][DBLP]
    ACM Multimedia, 2006, pp:8- [Conf]
  41. Jimin Feng, Samarjit Chakraborty, Bertil Schmidt, Weiguo Liu, Unmesh D. Bordoloi
    Fast Schedulability Analysis Using Commodity Graphics Hardware. [Citation Graph (0, 0)][DBLP]
    RTCSA, 2007, pp:400-408 [Conf]
  42. Gordon J. Brebner, Samarjit Chakraborty, Weng-Fai Wong
    Editorial for the Special Issue on Field Programmable Technology. [Citation Graph (0, 0)][DBLP]
    VLSI Signal Processing, 2007, v:47, n:1, pp:1-2 [Journal]

  43. Intra- and inter-processor hybrid performance modeling for MPSoC architectures. [Citation Graph (, )][DBLP]


  44. Cache-aware optimization of BAN applications. [Citation Graph (, )][DBLP]


  45. Performance debugging of Esterel specifications. [Citation Graph (, )][DBLP]


  46. Fast model-based test case classification for performance analysis of multimedia MPSoC platforms. [Citation Graph (, )][DBLP]


  47. Control theory-based DVS for interactive 3D games. [Citation Graph (, )][DBLP]


  48. Evaluating design trade-offs in customizable processors. [Citation Graph (, )][DBLP]


  49. Designing heterogeneous ECU networks via compact architecture encoding and hybrid timing analysis. [Citation Graph (, )][DBLP]


  50. Context-sensitive timing analysis of Esterel programs. [Citation Graph (, )][DBLP]


  51. Timing analysis of esterel programs on general-purpose multiprocessors. [Citation Graph (, )][DBLP]


  52. Formal Methods in System and MpSoC Performance Analysis and Optimisation. [Citation Graph (, )][DBLP]


  53. Constant-time admission control for Deadline Monotonic tasks. [Citation Graph (, )][DBLP]


  54. Cache-Aware Timing Analysis of Streaming Applications. [Citation Graph (, )][DBLP]


  55. Constant-Time Admission Control for Partitioned EDF. [Citation Graph (, )][DBLP]


  56. 2009 IEEE/ACM/IFIP 7th workshop on embedded systems for Real-Time multimedia (ESTIMedia 2009). [Citation Graph (, )][DBLP]


  57. Robust image processing for an omnidirectional camera-based smart car door. [Citation Graph (, )][DBLP]


  58. Multimedia power management on a platter: from audio to video & games. [Citation Graph (, )][DBLP]


  59. A Hybrid DVS Scheme for Interactive 3D Games. [Citation Graph (, )][DBLP]


  60. Schedulability Analysis of MSC-based System Models. [Citation Graph (, )][DBLP]


  61. Performance Debugging of Real-Time Systems Using Multicriteria Schedulability Analysis. [Citation Graph (, )][DBLP]


  62. Lightweight Modeling of Complex State Dependencies in Stream Processing Systems. [Citation Graph (, )][DBLP]


  63. Composing Functional and State-Based Performance Models for Analyzing Heterogeneous Real-Time Systems. [Citation Graph (, )][DBLP]


  64. Multiprocessor Extensions to Real-Time Calculus. [Citation Graph (, )][DBLP]


  65. A Multi-mode Real-Time Calculus. [Citation Graph (, )][DBLP]


  66. Timing Analysis of Mixed Time/Event-Triggered Multi-Mode Systems. [Citation Graph (, )][DBLP]


  67. Power Management of Interactive 3D Games Using Frame Structures. [Citation Graph (, )][DBLP]


  68. Watermarking Video Clips with Workload Information for DVS. [Citation Graph (, )][DBLP]


  69. Programming and Performance Modelling of Automotive ECU Networks. [Citation Graph (, )][DBLP]


  70. Power Management for Mobile Multimedia: From Audio to Video & Games. [Citation Graph (, )][DBLP]


  71. Accelerating System-Level Design Tasks Using Commodity Graphics Hardware: A Case Study. [Citation Graph (, )][DBLP]


  72. Path-Constrained Relaxed Schedulability Analysis. [Citation Graph (, )][DBLP]


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