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Manfred Schimmler: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Viktor Bunimov, Manfred Schimmler
    Area and Time Efficient Modular Multiplication of Large Integers. [Citation Graph (0, 0)][DBLP]
    ASAP, 2003, pp:400-0 [Conf]
  2. Manfred Schimmler, Christoph Starke
    A Correction Network for N-Sorters. [Citation Graph (0, 0)][DBLP]
    AWOC, 1988, pp:444-455 [Conf]
  3. Viktor Bunimov, Manfred Schimmler
    Completely Redundant Modular Exponentiation by Operand Changing. [Citation Graph (0, 0)][DBLP]
    CDES, 2005, pp:224-232 [Conf]
  4. Sandeep Kumar, Christof Paar, Jan Pelzl, Gerd Pfeiffer, Manfred Schimmler
    A Configuration Concept for a Massively Parallel FPGA Architecture. [Citation Graph (0, 0)][DBLP]
    CDES, 2006, pp:207-212 [Conf]
  5. Sandeep Kumar, Christof Paar, Jan Pelzl, Gerd Pfeiffer, Manfred Schimmler
    Breaking Ciphers with COPACOBANA - A Cost-Optimized Parallel Code Breaker. [Citation Graph (0, 0)][DBLP]
    CHES, 2006, pp:101-118 [Conf]
  6. Viktor Bunimov, Manfred Schimmler
    High Radix Modular Multiplication of Large Integers Optimised with Respect to Area and Time. [Citation Graph (0, 0)][DBLP]
    ESA/VLSI, 2004, pp:427-433 [Conf]
  7. Viktor Bunimov, Manfred Schimmler, Wolfgang Bziuk
    Key Generation for Secure High Speed Communication. [Citation Graph (0, 0)][DBLP]
    Security and Management, 2003, pp:570-576 [Conf]
  8. Viktor Bunimov, Manfred Schimmler
    Efficient Parallel Multiplication Algorithm for Large Integres. [Citation Graph (0, 0)][DBLP]
    Euro-Par, 2003, pp:923-928 [Conf]
  9. Manfred Schimmler
    Architectures and Algorithms for Multimedia Applications. [Citation Graph (0, 0)][DBLP]
    Euro-Par, 2000, pp:1085- [Conf]
  10. Bertil Schmidt, Manfred Schimmler
    A Parallel Accelerator Architecture for Multimedia Video Compression. [Citation Graph (0, 0)][DBLP]
    Euro-Par, 1999, pp:950-960 [Conf]
  11. Bertil Schmidt, Heiko Schröder, Manfred Schimmler
    Scanning Biosequence Databases on a Hybrid Parallel Architecture. [Citation Graph (0, 0)][DBLP]
    Euro-Par, 2001, pp:360-370 [Conf]
  12. Bertil Schmidt, Manfred Schimmler, Heiko Schröder
    Morphological Hough Transform on the Instruction Systolic Array. [Citation Graph (0, 0)][DBLP]
    Euro-Par, 1997, pp:798-806 [Conf]
  13. Bertil Schmidt, Manfred Schimmler, Heiko Schröder
    Long Operand Arithmetic on Instruction Systolic Computer Architectures and Its Application in RSA Cryptography. [Citation Graph (0, 0)][DBLP]
    Euro-Par, 1998, pp:916-922 [Conf]
  14. Sandeep Kumar, Christof Paar, Jan Pelzl, Gerd Pfeiffer, Manfred Schimmler
    COPACOBANA A Cost-Optimized Special-Purpose Hardware for Code-Breaking. [Citation Graph (0, 0)][DBLP]
    FCCM, 2006, pp:311-312 [Conf]
  15. Hans-Werner Lang, Manfred Schimmler, Hartmut Schmeck, Heiko Schröder
    A Method for Realistic Comparisons of Sorting Algorithms for VLSI. [Citation Graph (0, 0)][DBLP]
    FODO, 1985, pp:309-316 [Conf]
  16. David Narh Amanor, Viktor Bunimov, Christof Paar, Jan Pelzl, Manfred Schimmler
    Efficient Hardware Architectures for Modular Multiplication on FPGAs. [Citation Graph (0, 0)][DBLP]
    FPL, 2005, pp:539-542 [Conf]
  17. Manfred Schimmler, Hans-Werner Lang, Rüdiger Maaß
    The Instruction Systolic Array - Implementation of a Low-Cost Parallel Architecture as Add-On Board for Personal Computers. [Citation Graph (0, 0)][DBLP]
    HPCN, 1994, pp:487-488 [Conf]
  18. Hans-Werner Lang, Manfred Schimmler, Hartmut Schmeck, Heiko Schröder
    A Fast Sorting Algorithm for VLSI. [Citation Graph (0, 0)][DBLP]
    ICALP, 1983, pp:408-419 [Conf]
  19. Michael Phieler, Manfred Schimmler, Hartmut Schmeck
    A Reconfigurable Instruction Systolic Array. [Citation Graph (0, 0)][DBLP]
    Fault-Tolerant Computing Systems, 1991, pp:312-323 [Conf]
  20. Stefan Baumgart, Begona Toledo, Karin Spors, Manfred Schimmler
    PLUG: An Agent Based Prototype Validation of CAD-Constructions. [Citation Graph (0, 0)][DBLP]
    IKE, 2006, pp:183-190 [Conf]
  21. Bertil Schmidt, Heiko Schröder, Manfred Schimmler
    Massively Parallel Solutions for Molecular Sequence Analysis. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2002, pp:- [Conf]
  22. Manfred Schimmler, Viktor Bunimov
    Fast Modular Multiplication by Operand Changing. [Citation Graph (0, 0)][DBLP]
    ITCC (2), 2004, pp:518-524 [Conf]
  23. Gerd Pfeiffer, Heinz Kreft, Manfred Schimmler
    Hardware Enhanced Biosequence Alignment. [Citation Graph (0, 0)][DBLP]
    METMBS, 2005, pp:11-17 [Conf]
  24. Bertil Schmidt, Heiko Schröder, Manfred Schimmler
    Protein Sequence Comparison on the Instruction Systolic Array. [Citation Graph (0, 0)][DBLP]
    PaCT, 2001, pp:498-509 [Conf]
  25. Manfred Schimmler, Bertil Schmidt, Hans-Werner Lang
    Design of a Bit-Serial Floating Point Unit for a Fine Grained Parallel Processor Array. [Citation Graph (0, 0)][DBLP]
    PDPTA, 2003, pp:255-261 [Conf]
  26. Manfred Schimmler, Viktor Bunimov
    A Simple Circuit to Reduce the Search Range for Large Prime Numbers. [Citation Graph (0, 0)][DBLP]
    VLSI, 2003, pp:285-291 [Conf]
  27. Manfred Schimmler, Hartmut Schmeck
    A Fault Tolerant and High Speed Instruction Systolic Array. [Citation Graph (0, 0)][DBLP]
    VLSI, 1991, pp:471-480 [Conf]
  28. Manfred Schimmler, Bertil Schmidt, Hans-Werner Lang, Sven Heithecker
    An Area-Efficient Bit-Serial Integer Multiplier. [Citation Graph (0, 0)][DBLP]
    VLSI, 2003, pp:131-137 [Conf]
  29. Manfred Schimmler, Heiko Schröder
    A Simple Systolic Method to Find all Bridges of an Undirected Graph. [Citation Graph (0, 0)][DBLP]
    WG, 1988, pp:262-267 [Conf]
  30. Bertil Schmidt, Manfred Schimmler, Heiko Schröder
    A Morphological Approach to Hough Transform on an Instruction Systolic Array. [Citation Graph (0, 0)][DBLP]
    Computers and Artificial Intelligence, 1999, v:18, n:6, pp:- [Journal]
  31. Bertil Schmidt, Heiko Schröder, Manfred Schimmler
    Tomographic Image Reconstruction on the Instruction Systolic Array. [Citation Graph (0, 0)][DBLP]
    Computers and Artificial Intelligence, 2001, v:20, n:1, pp:- [Journal]
  32. Bertil Schmidt, Heiko Schröder, Manfred Schimmler
    A hybrid architecture for bioinformatics. [Citation Graph (0, 0)][DBLP]
    Future Generation Comp. Syst., 2002, v:18, n:6, pp:855-862 [Journal]
  33. Manfred Schimmler, Bertil Schmidt, Hans-Werner Lang
    A bit-serial floating-point unit for a massively parallel system on a chip. [Citation Graph (0, 0)][DBLP]
    Parallel Algorithms Appl., 2004, v:19, n:2-3, pp:79-95 [Journal]
  34. Manfred Kunde, Hans-Werner Lang, Manfred Schimmler, Hartmut Schmeck, Heiko Schröder
    The instruction systolic array and its relation to other models of parallel computers. [Citation Graph (0, 0)][DBLP]
    Parallel Computing, 1988, v:7, n:1, pp:25-39 [Journal]
  35. E. V. Krishnamurthy, Manfred Kunde, Manfred Schimmler, Heiko Schröder
    Systolic algorithm for tensor products of matrices: implementation and applications. [Citation Graph (0, 0)][DBLP]
    Parallel Computing, 1990, v:13, n:3, pp:301-308 [Journal]
  36. Manfred Schimmler
    Parallel strong orientation on a mesh connected computer. [Citation Graph (0, 0)][DBLP]
    Parallel Computing, 1991, v:17, n:6-7, pp:657-664 [Journal]
  37. Manfred Schimmler, Heiko Schröder
    A simple systolic method to find all bridges of an undirected graph. [Citation Graph (0, 0)][DBLP]
    Parallel Computing, 1989, v:12, n:1, pp:107-111 [Journal]
  38. Manfred Schimmler, Christoph Starke
    A Correction Network for N-Sorters. [Citation Graph (0, 0)][DBLP]
    SIAM J. Comput., 1989, v:18, n:6, pp:1179-1187 [Journal]
  39. Hans-Werner Lang, Manfred Schimmler, Hartmut Schmeck, Heiko Schröder
    Systolic Sorting on a Mesh-Connected Network. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1985, v:34, n:7, pp:652-658 [Journal]

  40. A Specification Methodology for the Optimal Layout of a 2-Stage Interconnect Bus for Massively Parallel Architectures. [Citation Graph (, )][DBLP]


  41. Enhancing COPACOBANA for advanced applications in cryptography and cryptanalysis. [Citation Graph (, )][DBLP]


  42. A Massively Parallel Architecture for Bioinformatics. [Citation Graph (, )][DBLP]


  43. Parallel Computing with Low-Cost FPGAs: A Framework for COPACOBANA. [Citation Graph (, )][DBLP]


  44. Massively Parallelized DNA Motif Search on the Reconfigurable Hardware Platform COPACOBANA. [Citation Graph (, )][DBLP]


  45. BMA - Boolean Matrices as Model for Motif Kernels. [Citation Graph (, )][DBLP]


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