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Jarmo Takala: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Adrian Burian, Perttu Salmela, Jarmo Takala
    Complex Fixed-Point Matrix Inversion Using Transport Triggered Architecture. [Citation Graph (0, 0)][DBLP]
    ASAP, 2005, pp:107-112 [Conf]
  2. Tuomas Järvinen, Perttu Salmela, Harri Sorokin, Jarmo Takala
    Stride Permutation Networks for Array Processors. [Citation Graph (0, 0)][DBLP]
    ASAP, 2004, pp:376-386 [Conf]
  3. Perttu Salmela, Tuomas Järvinen, Teemu Sipilä, Jarmo Takala
    256-State Rate 1/2 Viterbi Decoder on TTA Processor. [Citation Graph (0, 0)][DBLP]
    ASAP, 2005, pp:370-378 [Conf]
  4. Jari Nikara, Stamatis Vassiliadis, Jarmo Takala, Mihai Sima, Petri Liuha
    Parallel Multiple-Symbol Variable-Length Decoding. [Citation Graph (0, 0)][DBLP]
    ICCD, 2002, pp:126-131 [Conf]
  5. Jouko O. Viitanen, Jarmo Takala
    SIMD Parallel Calculation of Distance Transformations. [Citation Graph (0, 0)][DBLP]
    ICIP (3), 1994, pp:645-649 [Conf]
  6. Adrian Burian, Jarmo Takala
    A recurrent neural network for 1-D phase retrieval. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2003, pp:729-732 [Conf]
  7. Adrian Burian, Jarmo Takala, Marina Dana Topa
    Parallel iterations for recursive median filter. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2003, pp:488-491 [Conf]
  8. Jari Heikkinen, Andrea G. M. Cilio, Jarmo Takala, Henk Corporaal
    Dictionary-based program compression on transport triggered architectures. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2005, pp:1122-1125 [Conf]
  9. Jarmo Takala, Tuomas Järvinen, Harri Sorokin
    Conflict-free parallel memory access scheme for FFT processors. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2003, pp:524-527 [Conf]
  10. Riku Uusikartano, Jarmo Takala
    A low-power fractional decimator architecture for an IF-sampling dual-mode receiver. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2004, pp:589-592 [Conf]
  11. Mikko Ylinen, Adrian Burian, Jarmo Takala
    Direct versus iterative methods for fixed-point implementation of matrix inversion. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2004, pp:225-228 [Conf]
  12. Jari Nikara, Jarmo Takala, David Akopian, Jukka Saarinen
    Pipeline architecture for DCT/IDCT. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:902-905 [Conf]
  13. T. S. Jarvinen, J. H. Takala, David Akopian, J. P. P. Saarinen
    Register-based multi-port perfect shuffle networks. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:306-309 [Conf]
  14. Adrian Burian, Jarmo Takala
    VLSI-efficient implementation of full adder-based median filter. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2004, pp:817-820 [Conf]
  15. J. H. Takala, T. S. Jarvinen, J. A. Nikara
    Register-based reordering networks for matrix transpose. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2002, pp:874-877 [Conf]
  16. Jari Heikkinen, Tommi Rantanen, Andrea G. M. Cilio, Jarmo Takala, Henk Corporaal
    Evaluating Template-Based Instruction Compression on Transport Triggered Architectures. [Citation Graph (0, 0)][DBLP]
    IWSOC, 2003, pp:192-195 [Conf]
  17. Jussi Nykänen, Harri Klapuri, Jarmo Takala
    Mapping Action Systems to Hardware Descriptions. [Citation Graph (0, 0)][DBLP]
    PDPTA, 2003, pp:1407-1412 [Conf]
  18. Teemu Pitkänen, Risto Mäkinen, Jari Heikkinen, Tero Partanen, Jarmo Takala
    Low-Power, High-Performance TTA Processor for 1024-Point Fast Fourier Transform. [Citation Graph (0, 0)][DBLP]
    SAMOS, 2006, pp:227-236 [Conf]
  19. Teemu Pitkänen, Tommi Rantanen, Andrea G. M. Cilio, Jarmo Takala
    Hardware Cost Estimation for Application-Specific Processor Design. [Citation Graph (0, 0)][DBLP]
    SAMOS, 2005, pp:212-221 [Conf]
  20. Jari Heikkinen, Jarmo Takala
    Effects of Program Compression. [Citation Graph (0, 0)][DBLP]
    SAMOS, 2006, pp:259-268 [Conf]
  21. Tuomas Järvinen, Jarmo Takala
    Register-Based Permutation Networks for Stride Permutations. [Citation Graph (0, 0)][DBLP]
    SAMOS, 2004, pp:108-117 [Conf]
  22. Perttu Salmela, Pekka Jääskeläinen, Tuomas Järvinen, Jarmo Takala
    Software Pipelining Support for Transport Triggered Architecture Processors. [Citation Graph (0, 0)][DBLP]
    SAMOS, 2006, pp:237-247 [Conf]
  23. Daniel Iancu, Hua Ye, Emanoil Surducan, Murugappan Senthilvelan, John Glossner, Vasile Surducan, Vladimir Kotlyar, Andrei Iancu, Gary Nacer, Jarmo Takala
    Software Implementation of WiMAX on the Sandbridge SandBlaster Platform. [Citation Graph (0, 0)][DBLP]
    SAMOS, 2006, pp:435-446 [Conf]
  24. Jarmo Takala, Konsta Punkka
    Scalable FFT Processors and Pipelined Butterfly Units. [Citation Graph (0, 0)][DBLP]
    SAMOS, 2004, pp:373-382 [Conf]
  25. Tuomas Järvinen, Perttu Salmela, Teemu Sipilä, Jarmo Takala
    In-Place Storage of Path Metrics in Viterbi Decoders. [Citation Graph (0, 0)][DBLP]
    VLSI-SOC, 2003, pp:295-300 [Conf]
  26. Jari Nikara, Stamatis Vassiliadis, Jarmo Takala, Petri Liuha
    FPGA-Based Variable Length Decoders. [Citation Graph (0, 0)][DBLP]
    VLSI-SOC, 2003, pp:437-441 [Conf]
  27. Jarmo Takala, Jouko O. Viitanen
    Distance Transform Algorithm for Bit-Serial SIMD Architectures. [Citation Graph (0, 0)][DBLP]
    Computer Vision and Image Understanding, 1999, v:74, n:2, pp:150-161 [Journal]
  28. Tuomas Järvinen, Perttu Salmela, Teemu Sipilä, Jarmo Takala
    Systematic approach for path metric access in Viterbi decoders. [Citation Graph (0, 0)][DBLP]
    IEEE Transactions on Communications, 2005, v:53, n:5, pp:755-759 [Journal]
  29. Jari Nikara, Stamatis Vassiliadis, Jarmo Takala, Petri Liuha
    Multiple-symbol parallel decoding for variable length codes. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2004, v:12, n:7, pp:676-685 [Journal]
  30. Jari Nikara, Jarmo Takala, Jaakko Astola
    Discrete cosine and sine transforms - regular algorithms and pipeline architectures. [Citation Graph (0, 0)][DBLP]
    Signal Processing, 2006, v:86, n:2, pp:230-249 [Journal]
  31. Tuomas Järvinen, Perttu Salmela, Konsta Punkka, Jarmo Takala
    Evaluation of stride permutation networks. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]
  32. Pekka Jääskeläinen, Vladimír Guzma, Jarmo Takala
    Resource Conflict Detection in Simulation of Function Unit Pipelines. [Citation Graph (0, 0)][DBLP]
    SAMOS, 2007, pp:233-240 [Conf]
  33. Teemu Pitkänen, Tero Partanen, Jarmo Takala
    Low-Power Twiddle Factor Unit for FFT Computation. [Citation Graph (0, 0)][DBLP]
    SAMOS, 2007, pp:65-74 [Conf]
  34. Jarno K. Tanskanen, Teemu Pitkänen, Risto Mäkinen, Jarmo Takala
    Parallel Memory Architecture for TTA Processor. [Citation Graph (0, 0)][DBLP]
    SAMOS, 2007, pp:273-282 [Conf]
  35. Jarmo Takala, Timo D. Hämäläinen, Andy D. Pimentel, Stamatis Vassiliadis
    Editorial. [Citation Graph (0, 0)][DBLP]
    Journal of Systems Architecture, 2007, v:53, n:8, pp:465- [Journal]
  36. Jari Heikkinen, Jarmo Takala
    Effects of program compression. [Citation Graph (0, 0)][DBLP]
    Journal of Systems Architecture, 2007, v:53, n:10, pp:679-688 [Journal]
  37. Jarmo Takala, Konsta Punkka
    Scalable FFT Processors and Pipelined Butterfly Units. [Citation Graph (0, 0)][DBLP]
    VLSI Signal Processing, 2006, v:43, n:2-3, pp:113-123 [Journal]

  38. Robust Adders Based on Quantum-Dot Cellular Automata. [Citation Graph (, )][DBLP]


  39. Reducing Context Switch Overhead with Compiler-Assisted Threading. [Citation Graph (, )][DBLP]


  40. SPICE Simulation of Analog Filters: A Method for Designing Digital Filters. [Citation Graph (, )][DBLP]


  41. Laplacian modeling of DCT coefficients for real-time encoding. [Citation Graph (, )][DBLP]


  42. Reliability of n-Bit Nanotechnology Adder. [Citation Graph (, )][DBLP]


  43. Impact of Software Bypassing on Instruction Level Parallelism and Register File Traffic. [Citation Graph (, )][DBLP]


  44. Efficient Reed-Solomon Iterative Decoder Using Galois Field Instruction Set. [Citation Graph (, )][DBLP]


  45. Arithmetic Design on Quantum-Dot Cellular Automata Nanotechnology. [Citation Graph (, )][DBLP]


  46. Programmable and Scalable Architecture for Graphics Processing Units. [Citation Graph (, )][DBLP]


  47. Radix-4 Recoded Multiplier on Quantum-Dot Cellular Automata. [Citation Graph (, )][DBLP]


  48. Fine-grained application-specific instruction set processor design for the K-best list sphere detector algorithm. [Citation Graph (, )][DBLP]


  49. Memory-Based List Updating for List Sphere Decoders. [Citation Graph (, )][DBLP]


  50. Synthesis of DSP Architectures Using Libraries of Coarse-Grain Configurations. [Citation Graph (, )][DBLP]


  51. Low-complexity polynomials modulo integer with linearly incremented variable. [Citation Graph (, )][DBLP]


  52. Reducing processor energy consumption by compiler optimization. [Citation Graph (, )][DBLP]


  53. Reconfigurable video decoder with transform acceleration. [Citation Graph (, )][DBLP]


  54. Complex-valued QR decomposition implementation for MIMO receivers. [Citation Graph (, )][DBLP]


  55. A detection algorithm for zero-quantized DCT coefficients in JPEG. [Citation Graph (, )][DBLP]


  56. Implementing communications systems on an SDR SoC. [Citation Graph (, )][DBLP]


  57. Low-power application-specific processor for FFT computations. [Citation Graph (, )][DBLP]


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