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Jim D. Garside: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

Aristides Efthymiou, Jim D. Garside, Ioannis Papaefstathiou
A Low-Power Processor Architecture Optimized forWireless Devices. [Citation Graph (0, 0)][DBLP]
ASAP, 2005, pp:185-190 [Conf]
Jordi Cortadella, Alexandre Yakovlev, Jim D. Garside
T8: Logic Design of Asynchronous Circuits. [Citation Graph (0, 0)][DBLP]
ASP-DAC, 2002, pp:26-30 [Conf]
Mike J. G. Lewis, Jim D. Garside, L. E. M. Brackenbury
Reconfigurable Latch Controllers for Low Power Asynchronous Circuits. [Citation Graph (0, 0)][DBLP]
ASYNC, 1999, pp:27-35 [Conf]
Jim D. Garside, W. J. Bainbridge, Andrew Bardsley, David M. Clark, David A. Edwards, Stephen B. Furber, David W. Lloyd, S. Mohammadi, J. S. Pepper, Steve Temple, J. V. Woods, Jianwei Liu, O. Petli
AMULET3i - An Asynchronous System-on-Chip. [Citation Graph (0, 0)][DBLP]
ASYNC, 2000, pp:162-175 [Conf]
D. A. Gilbert, Jim D. Garside
A Result Forwarding Mechanism for Asynchronous Pipelined Systems. [Citation Graph (0, 0)][DBLP]
ASYNC, 1997, pp:2-11 [Conf]
W. J. Bainbridge, Andrew Bardsley, Steve Temple, Jim D. Garside, P. A. Riocreux, Luis A. Plana
SPA - A Synthesisable Amulet Core for Smartcard pplications. [Citation Graph (0, 0)][DBLP]
ASYNC, 2002, pp:201-210 [Conf]
Daranee Hormdee, Jim D. Garside
AMULET3i Cache Architecture. [Citation Graph (0, 0)][DBLP]
ASYNC, 2001, pp:152-161 [Conf]
Aristides Efthymiou, Jim D. Garside
Adaptive Pipeline Structures fo Speculation Control. [Citation Graph (0, 0)][DBLP]
ASYNC, 2003, pp:46-55 [Conf]
Stephen B. Furber, Jim D. Garside, Steve Temple, Jianwei Liu, P. Day, N. C. Paver
AMULET2e: An Asynchronous Embedded Controller. [Citation Graph (0, 0)][DBLP]
ASYNC, 1997, pp:290-0 [Conf]
Aristides Efthymiou, W. Suntiamorntut, Jim D. Garside, L. E. M. Brackenbury
An Asynchronous, Iterative Implementation of the Original Booth Multiplication Algorithm. [Citation Graph (0, 0)][DBLP]
ASYNC, 2004, pp:207-215 [Conf]
Jim D. Garside, Stephen B. Furber, S.-H. Chung
AMULET3 Revealed. [Citation Graph (0, 0)][DBLP]
ASYNC, 1999, pp:51-59 [Conf]
David W. Lloyd, Jim D. Garside
A Practical Comparison of Asynchronous Design Styles. [Citation Graph (0, 0)][DBLP]
ASYNC, 2001, pp:36-45 [Conf]
David W. Lloyd, Jim D. Garside, D. A. Gilbert
Memory Faults in Asynchronous Microprocessors. [Citation Graph (0, 0)][DBLP]
ASYNC, 1999, pp:71-0 [Conf]
Stephen B. Furber, P. Day, Jim D. Garside, N. C. Paver, J. V. Woods
AMULET1: A Micropipelined ARM. [Citation Graph (0, 0)][DBLP]
COMPCON, 1994, pp:476-485 [Conf]
Daranee Hormdee, Jim D. Garside, Stephen B. Furber
An Asynchronous Victim Cache. [Citation Graph (0, 0)][DBLP]
DSD, 2002, pp:4-11 [Conf]
A. Robinson, Jim D. Garside
Sensitive registers: a technique for reducing the fetch bandwidth in low-power microprocessors. [Citation Graph (0, 0)][DBLP]
ACM Great Lakes Symposium on VLSI, 2007, pp:138-143 [Conf]
Stephen B. Furber, P. Day, Jim D. Garside, N. C. Paver, Steve Temple, J. V. Woods
The Design and Evaluation of an Asynchronous Microprocessor. [Citation Graph (0, 0)][DBLP]
ICCD, 1994, pp:217-220 [Conf]
Stephen B. Furber, David A. Edwards, Jim D. Garside
AMULET3: A 100 MIPS Asynchronous Embedded Processor. [Citation Graph (0, 0)][DBLP]
ICCD, 2000, pp:329-334 [Conf]
Aristides Efthymiou, Jim D. Garside
Adaptive Pipeline Depth Control for Processor Power-Management. [Citation Graph (0, 0)][DBLP]
ICCD, 2002, pp:454-457 [Conf]
N. C. Paver, P. Day, Stephen B. Furber, Jim D. Garside, J. V. Woods
Register Locking in an Asynchronous Microprocessor. [Citation Graph (0, 0)][DBLP]
ICCD, 1992, pp:351-355 [Conf]
Jim D. Garside
A CMOS VLSI Implementation of an Asynchronous ALU. [Citation Graph (0, 0)][DBLP]
Asynchronous Design Methodologies, 1993, pp:181-192 [Conf]
Aristides Efthymiou, Jim D. Garside
An adaptive serial-parallel CAM architecture for low-power cache blocks. [Citation Graph (0, 0)][DBLP]
ISLPED, 2002, pp:136-141 [Conf]
Stephen B. Furber, P. Day, Jim D. Garside, N. C. Paver, J. V. Woods
A micropipelined ARM. [Citation Graph (0, 0)][DBLP]
VLSI, 1993, pp:211-220 [Conf]
C. Brej, Jim D. Garside
A Quasi-Delay-Insensitive Method to Overcome Transistor Variation. [Citation Graph (0, 0)][DBLP]
VLSI Design, 2005, pp:368-373 [Conf]
Jordi Cortadella, Alexandre Yakovlev, Jim D. Garside
Logic Design of Asynchronous Circuits (Tutorial Abstract). [Citation Graph (0, 0)][DBLP]
VLSI Design, 2002, pp:26-0 [Conf]
Stephen B. Furber, Aristides Efthymiou, Jim D. Garside, David W. Lloyd, Mike J. G. Lewis, Steve Temple
Power Management in the Amulet Microprocessors. [Citation Graph (0, 0)][DBLP]
IEEE Design & Test of Computers, 2001, v:18, n:2, pp:42-52 [Journal]
J. V. Woods, P. Day, Stephen B. Furber, Jim D. Garside, N. C. Paver, Steve Temple
AMULET1: A Asynchronous ARM Microprocessor. [Citation Graph (0, 0)][DBLP]
IEEE Trans. Computers, 1997, v:46, n:4, pp:385-398 [Journal]
Aristides Efthymiou, Jim D. Garside
A CAM with mixed serial-parallel comparison for use in low energy caches. [Citation Graph (0, 0)][DBLP]
IEEE Trans. VLSI Syst., 2004, v:12, n:3, pp:325-329 [Journal]
Daranee Hormdee, Jim D. Garside, Stephen B. Furber
An asynchronous copy-back cache architecture. [Citation Graph (0, 0)][DBLP]
Microprocessors and Microsystems, 2003, v:27, n:10, pp:485-500 [Journal]
Luis A. Plana, P. A. Riocreux, W. J. Bainbridge, Andrew Bardsley, Steve Temple, Jim D. Garside, Z. C. Yu
SPA - a secure Amulet core for smartcard applications. [Citation Graph (0, 0)][DBLP]
Microprocessors and Microsystems, 2003, v:27, n:9, pp:431-446 [Journal]
An adaptive bloom filter cache partitioning scheme for multicore architectures. [Citation Graph (, )][DBLP]

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