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Ioannis Papaefstathiou: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Aristides Efthymiou, Jim D. Garside, Ioannis Papaefstathiou
    A Low-Power Processor Architecture Optimized forWireless Devices. [Citation Graph (0, 0)][DBLP]
    ASAP, 2005, pp:185-190 [Conf]
  2. George Kornaros, Theofanis Orphanoudakis, Ioannis Papaefstathiou
    GFS: An Efficient Implementation of Fair Scheduling for Mult-Gigabit Packet Networks. [Citation Graph (0, 0)][DBLP]
    ASAP, 2003, pp:389-399 [Conf]
  3. George Kornaros, Ioannis Papaefstathiou, Aristides Nikologiannis, Nicholaos Zervos
    A fully-programmable memory management system optimizing queue handling at multi-gigabit rates. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:54-59 [Conf]
  4. Ioannis Papaefstathiou, George Kornaros, Nicholaos Zervos
    Software Processing Performance in Network Processors. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:186-191 [Conf]
  5. Ioannis Papaefstathiou, Theofanis Orphanoudakis, George Kornaros, Christopher Kachris, Ioannis Mavroidis, Aristides Nikologiannis
    Queue Management in Network Processors. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:112-117 [Conf]
  6. Vassilis Papaefstathiou, Ioannis Papaefstathiou
    A hardware-engine for layer-2 classification in low-storage, ultra-high bandwidth environments. [Citation Graph (0, 0)][DBLP]
    DATE Designers' Forum, 2006, pp:112-117 [Conf]
  7. Ioannis Papaefstathiou
    Compressing ATM Streams On-Line. [Citation Graph (0, 0)][DBLP]
    Data Compression Conference, 1999, pp:543- [Conf]
  8. Ioannis Papaefstathiou, George Kornaros, Nikolaos Chrysos
    A buffered crossbar-based chip interconnection framework supporting quality of service. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2007, pp:90-95 [Conf]
  9. George Kornaros, Ioannis Papaefstathiou
    An Innovative Resource Management Scheme for Multi-gigabit Networking Systems. [Citation Graph (0, 0)][DBLP]
    HSNMC, 2003, pp:165-175 [Conf]
  10. George Kornaros, Theofanis Orphanoudakis, Yannis Papaefstathiou
    Active flow identifiers for scalable, QoS scheduling in 10-Gbps network processors. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2003, pp:97-100 [Conf]
  11. Ioannis Papaefstathiou, Helen-Catherine Leligou, Theofanis Orphanoudakis, George Kornaros, Nicholaos Zervos, George E. Konstantoulakis
    An innovative scheduling scheme for high-speed network processors. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2003, pp:93-96 [Conf]
  12. Ioannis Papaefstathiou
    Measurement Based Connection Admission Control Algorithm for ATM Networks that Use Low Level Compression. [Citation Graph (0, 0)][DBLP]
    IS&N, 2000, pp:49-60 [Conf]
  13. Ioannis Papaefstathiou
    Titan II : An IPComp Processor for 10Gbit/sec networks. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2003, pp:234-235 [Conf]
  14. Vassilis Papaefstathiou, Ioannis Papaefstathiou
    A Memory Efficient, 100 Gb/sec MAC Classification Engine. [Citation Graph (0, 0)][DBLP]
    LCN, 2005, pp:470-471 [Conf]
  15. Ioannis Papaefstathiou
    Titan II: An IPcomp Processor for 10-Gbps Networks. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2004, v:21, n:6, pp:514-523 [Journal]
  16. Ioannis Papaefstathiou
    Low Level Hardware Compression for Multi-gigabit Networks. [Citation Graph (0, 0)][DBLP]
    Journal of Circuits, Systems, and Computers, 2004, v:13, n:6, pp:1307-1320 [Journal]
  17. Ioannis Papaefstathiou, Nikos A. Nikolaou, Bharat T. Doshi, Eric Grosse
    Guest Editors' Introduction: Network Processors for Future High-End Systems and Applications. [Citation Graph (0, 0)][DBLP]
    IEEE Micro, 2004, v:24, n:5, pp:7-9 [Journal]
  18. Ioannis Papaefstathiou, Stylianos Perissakis, Theofanis Orphanoudakis, Nikos A. Nikolaou, George Kornaros, Nicholas Zervos, George E. Konstantoulakis, Dionisios N. Pnevmatikatos, Kyriakos Vlachos
    PRO3: A Hybrid NPU Architecture. [Citation Graph (0, 0)][DBLP]
    IEEE Micro, 2004, v:24, n:5, pp:20-33 [Journal]
  19. Ioannis Papaefstathiou, Vassilis Papaefstathiou, C. Sotiriou
    Design-space exploration of the most widely used cryptography algorithms. [Citation Graph (0, 0)][DBLP]
    Microprocessors and Microsystems, 2004, v:28, n:10, pp:561-571 [Journal]
  20. Aristides Nikologiannis, Ioannis Papaefstathiou, George Kornaros, Christopher Kachris
    An FPGA-based queue management system for high speed networking devices. [Citation Graph (0, 0)][DBLP]
    Microprocessors and Microsystems, 2004, v:28, n:5-6, pp:223-236 [Journal]
  21. Ioannis Mavroidis, Ioannis Papaefstathiou
    Efficient testbench code synthesis for a hardware emulator system. [Citation Graph (0, 0)][DBLP]
    DATE, 2007, pp:888-893 [Conf]
  22. Ioannis Papaefstathiou, Vassilis Papaefstathiou
    Memory-Efficient 5D Packet Classification At 40 Gbps. [Citation Graph (0, 0)][DBLP]
    INFOCOM, 2007, pp:1370-1378 [Conf]
  23. Ioannis Mavroidis, Ioannis Papaefstathiou, Dionisios N. Pnevmatikatos
    Hardware Implementation of 2-Opt Local Search Algorithm for the Traveling Salesman Problem. [Citation Graph (0, 0)][DBLP]
    IEEE International Workshop on Rapid System Prototyping, 2007, pp:41-47 [Conf]
  24. Vassilis Dimopoulos, Ioannis Papaefstathiou, Dionisios N. Pnevmatikatos
    A Memory-Efficient Reconfigurable Aho-Corasick FSM Implementation for Intrusion Detection Systems. [Citation Graph (0, 0)][DBLP]
    ICSAMOS, 2007, pp:186-193 [Conf]
  25. Ioannis Papaefstathiou
    Accelerating ATM: on-line compression of ATM streams. [Citation Graph (0, 0)][DBLP]
    IPCCC, 1999, pp:233-239 [Conf]
  26. Ioannis Papaefstathiou, Theofanis Orphanoudakis, George Kornaros, Christopher Kachris, Ioannis Mavroidis, Aristides Nikologiannis
    Queue Management in Network Processors [Citation Graph (0, 0)][DBLP]
    CoRR, 2007, v:0, n:, pp:- [Journal]

  27. Heavily Reducing WSNs' Energy Consumption by Employing Hardware-Based Compression. [Citation Graph (, )][DBLP]


  28. Design and implementation of a database filter for BLAST acceleration. [Citation Graph (, )][DBLP]


  29. A Fast FPGA-Based 2-Opt Solver for Small-Scale Euclidean Traveling Salesman Problem. [Citation Graph (, )][DBLP]


  30. Titan-R: A Reconfigurable Hardware Implementation of a High-Speed Compressor. [Citation Graph (, )][DBLP]


  31. A Memory-Efficient FPGA-based Classification Engine. [Citation Graph (, )][DBLP]


  32. MPLEM: An 80-processor FPGA Based Multiprocessor System. [Citation Graph (, )][DBLP]


  33. High. [Citation Graph (, )][DBLP]


  34. Implementation of a genetic algorithm on a virtex-ii pro FPGA. [Citation Graph (, )][DBLP]


  35. A FPGA based coprocessor for gene finding using Interpolated Markov Model (IMM). [Citation Graph (, )][DBLP]


  36. Design space exploration of reconfigurable systems for calculating flying object's optimal noise reduction paths. [Citation Graph (, )][DBLP]


  37. A fast parallel matrix multiplication reconfigurable unit utilized in face recognitions systems. [Citation Graph (, )][DBLP]


  38. A self-reconfiguring architecture supporting multiple objective functions in genetic algorithms. [Citation Graph (, )][DBLP]


  39. A Multi Gigabit FPGA-Based 5-tuple Classification System. [Citation Graph (, )][DBLP]


  40. An Embedded Networking SoC for purely Ethernet MANs/WANs. [Citation Graph (, )][DBLP]


  41. Design and Implementation of an UWB Digital Transmitter Based on the Multiband OFDM Physical Layer Proposal. [Citation Graph (, )][DBLP]


  42. High-speed FPGA-based implementations of a Genetic Algorithm. [Citation Graph (, )][DBLP]


  43. Power Consumption Estimations vs Measurements for FPGA-Based Security Cores. [Citation Graph (, )][DBLP]


  44. Building an FoC Using Large, Buffered Crossbar Cores. [Citation Graph (, )][DBLP]


  45. Accelerating Emulation and Providing Full Chip Observability and Controllability. [Citation Graph (, )][DBLP]


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