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Pierre-Yves Calland: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Pierre-Yves Calland, Jack Dongarra, Yves Robert
    Tiling with limited resources. [Citation Graph (0, 0)][DBLP]
    ASAP, 1997, pp:229-238 [Conf]
  2. Pierre-Yves Calland, Alain Darte, Yves Robert, Frédéric Vivien
    On the Removal of Anti and Output Dependences. [Citation Graph (0, 0)][DBLP]
    ASAP, 1996, pp:353-364 [Conf]
  3. Pierre-Yves Calland, Tanguy Risset
    Precise Tiling for Uniform Loop Nests. [Citation Graph (0, 0)][DBLP]
    ASAP, 1995, pp:330-0 [Conf]
  4. Pierre-Yves Calland, Alain Darte, Yves Robert
    A New Guaranteed Heuristic for the Software Pipelining Problem. [Citation Graph (0, 0)][DBLP]
    International Conference on Supercomputing, 1996, pp:261-269 [Conf]
  5. Pierre-Yves Calland, Jack Dongarra, Yves Robert
    Tiling on systems with communication/computation overlap. [Citation Graph (0, 0)][DBLP]
    Concurrency - Practice and Experience, 1999, v:11, n:3, pp:139-153 [Journal]
  6. Pierre-Yves Calland, Alain Darte, Yves Robert, Frédéric Vivien
    On the Removal of Anti- and Output-Dependences. [Citation Graph (0, 0)][DBLP]
    International Journal of Parallel Programming, 1998, v:26, n:2, pp:285-312 [Journal]
  7. Pierre-Yves Calland, Alain Darte, Yves Robert, Frédéric Vivien
    Plugging Anti and Output Dependence Removal Techniques Into Loop Parallelization Algorithm. [Citation Graph (0, 0)][DBLP]
    Parallel Computing, 1997, v:23, n:1-2, pp:251-266 [Journal]
  8. Pierre-Yves Calland, Anne Mignotte, Olivier Peyran, Yves Robert, Frédéric Vivien
    Retiming DAGs [direct acyclic graph]. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1998, v:17, n:12, pp:1319-1325 [Journal]
  9. Pierre-Yves Calland, Alain Darte, Yves Robert
    Circuit Retiming Applied to Decomposed Software Pipelining. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Parallel Distrib. Syst., 1998, v:9, n:1, pp:24-35 [Journal]

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