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Author:
Hugo De Man: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Eddy de Greef, Francky Catthoor, Hugo De Man
    Array Placement for Storage Size Reduction in Embedded Multimedia Systems. [Citation Graph (0, 0)][DBLP]
    ASAP, 1997, pp:66-75 [Conf]
  2. Yajun Ha, Geert Vanmeerbeeck, Patrick Schaumont, Serge Vernalde, Marc Engels, Rudy Lauwereins, Hugo De Man
    Virtual Java/FPGA interface for networked reconfiguration. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2001, pp:558-563 [Conf]
  3. Koen Danckaert, Francky Catthoor, Hugo De Man
    A preprocessing step for global loop transformations for data transfer optimization. [Citation Graph (0, 0)][DBLP]
    CASES, 2000, pp:34-40 [Conf]
  4. Francky Catthoor, M. Van Swaalj, J. Rosseel, Hugo De Man
    Array design methodologies for real-time signal processing in the CATHEDRAL-IV synthesis environment. [Citation Graph (0, 0)][DBLP]
    Algorithms and Parallel VLSI Architectures, 1991, pp:211-222 [Conf]
  5. M. Van Swaalj, Francky Catthoor, Hugo De Man
    Signal analysis and signal transformations for ASIC regular array architecture synthesis. [Citation Graph (0, 0)][DBLP]
    Algorithms and Parallel VLSI Architectures, 1991, pp:223-232 [Conf]
  6. Koen Danckaert, Francky Catthoor, Hugo De Man
    System level memory optimization for hardware-software co-design. [Citation Graph (0, 0)][DBLP]
    CODES, 1997, pp:55-64 [Conf]
  7. Dirk Desmet, Michiel Esvelt, Prabhat Avasare, Diederik Verkest, Hugo De Man
    Timed executable system specification of an ADSL modem using a C++ based design environment: a case study. [Citation Graph (0, 0)][DBLP]
    CODES, 1999, pp:38-42 [Conf]
  8. Peter Marwedel, Daniel Gajski, Erwin A. de Kock, Hugo De Man, Mariagiovanna Sami, Ingemar Söderquist
    Embedded systems education: how to teach the required skills? [Citation Graph (0, 0)][DBLP]
    CODES+ISSS, 2004, pp:254-255 [Conf]
  9. Bill Lin, Steven Vercauteren, Hugo De Man
    Embedded Architecture Co-Synthesis and System Integration. [Citation Graph (0, 0)][DBLP]
    CODES, 1996, pp:2-9 [Conf]
  10. Frederik Vermeulen, Francky Catthoor, Diederik Verkest, Hugo De Man
    Extended design reuse trade-offs in hardware-software architecture mapping. [Citation Graph (0, 0)][DBLP]
    CODES, 2000, pp:103-107 [Conf]
  11. Mustafa Badaroglu, Kris Tiri, Stéphane Donnay, Piet Wambacq, Hugo De Man, Ingrid Verbauwhede, Georges G. E. Gielen
    Clock tree optimization in synchronous CMOS digital circuits for substrate noise reduction using folding of supply current transients. [Citation Graph (0, 0)][DBLP]
    DAC, 2002, pp:399-404 [Conf]
  12. Ivo Bolsens, W. De Rammelaere, Luc J. M. Claesen, Hugo De Man
    Electrical Debugging of Synchronous MOS VLSI Circuits Exploiting Analysis of the Intended Logic Behaviour. [Citation Graph (0, 0)][DBLP]
    DAC, 1989, pp:513-518 [Conf]
  13. H. Cai, Stefaan Note, Paul Six, Hugo De Man
    A Data Path Layout Assembler for High Performance DSP Circuits. [Citation Graph (0, 0)][DBLP]
    DAC, 1990, pp:306-311 [Conf]
  14. Dirk Desmet, Diederik Verkest, Hugo De Man
    Operating system based software generation for systems-on-chip. [Citation Graph (0, 0)][DBLP]
    DAC, 2000, pp:396-401 [Conf]
  15. Werner Geurts, Francky Catthoor, Hugo De Man
    Time Constrained Allocation and Assignment Techniques for High Throughput Signal Processing. [Citation Graph (0, 0)][DBLP]
    DAC, 1992, pp:124-127 [Conf]
  16. Gert Goossens, Joos Vandewalle, Hugo De Man
    Loop Optimization in Register-Transfer Scheduling for DSP-Systems. [Citation Graph (0, 0)][DBLP]
    DAC, 1989, pp:826-831 [Conf]
  17. Hugo De Man
    Education for the Deep Submicron Age: Business as Usual? [Citation Graph (0, 0)][DBLP]
    DAC, 1997, pp:307-312 [Conf]
  18. Stefaan Note, Werner Geurts, Francky Catthoor, Hugo De Man
    Cathedral-III: Architecture-Driven High-level Synthesis for High Throughput DSP Applications. [Citation Graph (0, 0)][DBLP]
    DAC, 1991, pp:597-602 [Conf]
  19. Patrick Odent, Luc J. M. Claesen, Hugo De Man
    Feedback Loops and Large Subcircuits in the Multiprocessor Implementation of a Relaxation Based Circuit Simulator. [Citation Graph (0, 0)][DBLP]
    DAC, 1989, pp:25-30 [Conf]
  20. S. Perremans, Luc J. M. Claesen, Hugo De Man
    Static Timing Analysis of Dynamically Sensitizable Paths. [Citation Graph (0, 0)][DBLP]
    DAC, 1989, pp:568-573 [Conf]
  21. Geert Van der Plas, Mustafa Badaroglu, Gerd Vandersteen, Petr Dobrovolný, Piet Wambacq, Stéphane Donnay, Georges G. E. Gielen, Hugo De Man
    High-level simulation of substrate noise in high-ohmic substrates with interconnect and supply effects. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:854-859 [Conf]
  22. Shishpal Rawat, William H. Joyner Jr., John A. Darringer, Daniel Gajski, Pat O. Pistilli, Hugo De Man, Carl Harris, James Solomon
    Were the good old days all that good?: EDA then and now. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:543- [Conf]
  23. Julio Leao da Silva Jr., Chantal Ykman-Couvreur, Miguel Miranda, Kris Croes, Sven Wuytack, Gjalt G. de Jong, Francky Catthoor, Diederik Verkest, Paul Six, Hugo De Man
    Efficient System Exploration and Synthesis of Applications with Dynamic Data Storage and Intensive Data Transfer. [Citation Graph (0, 0)][DBLP]
    DAC, 1998, pp:76-81 [Conf]
  24. Paul Six, Luc J. M. Claesen, Jan M. Rabaey, Hugo De Man
    An intelligent module generator environment. [Citation Graph (0, 0)][DBLP]
    DAC, 1986, pp:730-735 [Conf]
  25. I. Vandeweerd, Kris Croes, Luc Rijnders, Paul Six, Hugo De Man
    REDUSA: Module Generation by Automatic Elimination of Superfluous Blocks in Regular Structures. [Citation Graph (0, 0)][DBLP]
    DAC, 1989, pp:694-697 [Conf]
  26. Steven Vercauteren, Bill Lin, Hugo De Man
    Constructing Application-Specific Heterogeneous Embedded Architectures from Custom HW/SW Applications. [Citation Graph (0, 0)][DBLP]
    DAC, 1996, pp:521-526 [Conf]
  27. Steven Vercauteren, Bill Lin, Hugo De Man
    A Strategy for Real-Time Kernel Support in Application-Specific HW/SW Embedded Architectures. [Citation Graph (0, 0)][DBLP]
    DAC, 1996, pp:678-683 [Conf]
  28. Eric Verlind, Tilman Kolks, Gjalt G. de Jong, Bill Lin, Hugo De Man
    A Time Abstraction Method for Efficient Verification of Communicating Systems. [Citation Graph (0, 0)][DBLP]
    DAC, 1994, pp:609-614 [Conf]
  29. Mustafa Badaroglu, Marc van Heijningen, Vincent Gravot, Stéphane Donnay, Hugo De Man, Georges G. E. Gielen, Marc Engels, Ivo Bolsens
    High-level simulation of substrate noise generation from large digital circuits with multiple supplies. [Citation Graph (0, 0)][DBLP]
    DATE, 2001, pp:326-330 [Conf]
  30. Mustafa Badaroglu, Piet Wambacq, Geert Van der Plas, Stéphane Donnay, Georges G. E. Gielen, Hugo De Man
    Digital Ground Bounce Reduction by Phase Modulation of the Clock. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:88-93 [Conf]
  31. Hugo De Man
    On Nanoscale Integration and Gigascale Complexity in the Post.Com World. [Citation Graph (0, 0)][DBLP]
    DATE, 2002, pp:12- [Conf]
  32. Wolfgang Eberle, Gerd Vandersteen, Piet Wambacq, Stéphane Donnay, Georges G. E. Gielen, Hugo De Man
    Behavioral Modeling and Simulation of a Mixed Analog/Digital Automatic Gain Control Loop in a 5 GHz WLAN Receiver. [Citation Graph (0, 0)][DBLP]
    DATE, 2003, pp:10642-10649 [Conf]
  33. Chidamber Kulkarni, C. Ghez, Miguel Miranda, Francky Catthoor, Hugo De Man
    Cache conscious data layout organization for embedded multimedia applications. [Citation Graph (0, 0)][DBLP]
    DATE, 2001, pp:686-693 [Conf]
  34. Bingfeng Mei, Serge Vernalde, Diederik Verkest, Hugo De Man, Rudy Lauwereins
    Exploiting Loop-Level Parallelism on Coarse-Grained Reconfigurable Architectures Using Modulo Scheduling. [Citation Graph (0, 0)][DBLP]
    DATE, 2003, pp:10296-10301 [Conf]
  35. Frederik Vermeulen, Francky Catthoor, Hugo De Man, Diederik Verkest
    Formalized Three-Layer System-Level Reuse Model and Methodology for Embedded Data-Dominated Applications. [Citation Graph (0, 0)][DBLP]
    DATE, 2000, pp:92-98 [Conf]
  36. Piet Wambacq, Stéphane Donnay, Hocine Ziad, Marc Engels, Hugo De Man, Ivo Bolsens
    A Single-Package Solution for Wireless Transceivers. [Citation Graph (0, 0)][DBLP]
    DATE, 1999, pp:425-0 [Conf]
  37. Chun Wong, Paul Marchal, Peng Yang, Francky Catthoor, Hugo De Man, Aggeliki Prayati, Nathalie Cossement, Rudy Lauwereins, Diederik Verkest
    Task concurrency management methodology summary. [Citation Graph (0, 0)][DBLP]
    DATE, 2001, pp:813- [Conf]
  38. Ingrid Verbauwhede, Frank Hoornaert, Joos Vandewalle, Hugo De Man
    Security Considerations in the Design and Implementation of a new DES chip. [Citation Graph (0, 0)][DBLP]
    EUROCRYPT, 1987, pp:287-300 [Conf]
  39. Koen Schoofs, Gert Goossens, Hugo De Man
    Signal Type Optimisation in the Design of Time-Multiplexed DSP Architectures. [Citation Graph (0, 0)][DBLP]
    EDAC-ETC-EUROASIC, 1994, pp:502-506 [Conf]
  40. F. Depuydt, Werner Geurts, Gert Goossens, Hugo De Man
    Optimal Scheduling and Software Pipelining of Repetitive Signal Flow Graphs with Delay Line Optimization. [Citation Graph (0, 0)][DBLP]
    EDAC-ETC-EUROASIC, 1994, pp:490-494 [Conf]
  41. Peter Vanbekbergen, Chantal Ykman-Couvreur, Bill Lin, Hugo De Man
    A Generalized Signal Transition Graph Model for Specification of Complex Interfaces. [Citation Graph (0, 0)][DBLP]
    EDAC-ETC-EUROASIC, 1994, pp:378-384 [Conf]
  42. Frank H. M. Franssen, Lode Nachtergaele, H. Samsom, Francky Catthoor, Hugo De Man
    Control flow optimization for fast system simulation and storage minimization. [Citation Graph (0, 0)][DBLP]
    EDAC-ETC-EUROASIC, 1994, pp:20-24 [Conf]
  43. Hugo De Man
    Rethinking Engineering Research and Education for Post-PC Systems-on-a-Chip. [Citation Graph (0, 0)][DBLP]
    EUROMICRO, 2000, pp:1018-0 [Conf]
  44. Koen Danckaert, Francky Catthoor, Hugo De Man
    System-Level Memory Management for Weakly Parallel Image Processing. [Citation Graph (0, 0)][DBLP]
    Euro-Par, Vol. II, 1996, pp:217-225 [Conf]
  45. Chidamber Kulkarni, Francky Catthoor, Hugo De Man
    Hardware Cache Optimization for Parallel Multimedia Applications. [Citation Graph (0, 0)][DBLP]
    Euro-Par, 1998, pp:923-932 [Conf]
  46. Yajun Ha, Radovan Hipik, Serge Vernalde, Diederik Verkest, Marc Engels, Rudy Lauwereins, Hugo De Man
    Adding Hardware Support to the HotSpot Virtual Machine for Domain Specific Applications. [Citation Graph (0, 0)][DBLP]
    FPL, 2002, pp:1135-1138 [Conf]
  47. Yajun Ha, Bingfeng Mei, Patrick Schaumont, Serge Vernalde, Rudy Lauwereins, Hugo De Man
    Development of a Design Framework for Platform-Independent Networked Reconfiguration of Software and Hardware. [Citation Graph (0, 0)][DBLP]
    FPL, 2001, pp:264-274 [Conf]
  48. Bingfeng Mei, Serge Vernalde, Diederik Verkest, Hugo De Man, Rudy Lauwereins
    ADRES: An Architecture with Tightly Coupled VLIW Processor and Coarse-Grained Reconfigurable Matrix. [Citation Graph (0, 0)][DBLP]
    FPL, 2003, pp:61-70 [Conf]
  49. Florin Balasa, Werner Geurts, Francky Catthoor, Hugo De Man
    Solving large scale assignment problems in high-level synthesis by approximative quadratic programming. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2001, pp:19-24 [Conf]
  50. Julio Leao da Silva Jr., Chantal Ykman-Couvreur, Bill Lin, Hugo De Man, Gjalt G. de Jong
    A System Design Methodology for Telecommunication Network Applications. [Citation Graph (0, 0)][DBLP]
    Great Lakes Symposium on VLSI, 1997, pp:64-69 [Conf]
  51. Florin Balasa, Francky Catthoor, Hugo De Man
    Exact evaluation of memory size for multi-dimensional signal processing systems. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1993, pp:669-672 [Conf]
  52. Florin Balasa, Francky Catthoor, Hugo De Man
    Dataflow-driven memory allocation for multi-dimensional signal processing systems. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1994, pp:31-34 [Conf]
  53. F. Depuydt, Gert Goossens, Hugo De Man
    Clustering Techniques for Register Optimization During Scheduling Preprocessing. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1991, pp:280-283 [Conf]
  54. Werner Geurts, Francky Catthoor, Hugo De Man
    Quadratic zero-one programming based synthesis of application specific data paths. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1993, pp:522-525 [Conf]
  55. Tilman Kolks, Bill Lin, Hugo De Man
    Sizing and verification of communication buffers for communicating processes. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1993, pp:660-664 [Conf]
  56. Peter Vanbekbergen, Francky Catthoor, Gert Goossens, Hugo De Man
    Optimized Synthesis of Asynchronous Control Circuits from Graph-Theoretic Specifications. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1990, pp:184-187 [Conf]
  57. Peter Vanbekbergen, Bill Lin, Gert Goossens, Hugo De Man
    A generalized state assignment theory for transformation on signal transition graphs. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1992, pp:112-117 [Conf]
  58. J. Vanhoof, Ivo Bolsens, Hugo De Man
    Compiling Multi-Dimensional Data Streams into Distributed DSP ASIC Memory. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1991, pp:272-275 [Conf]
  59. Mark Genoe, Luc J. M. Claesen, Hugo De Man
    A Parallel Method for Functional Verification of Medium and High Throughput DSP Synthesis. [Citation Graph (0, 0)][DBLP]
    ICCD, 1994, pp:460-463 [Conf]
  60. Mark Genoe, Luc J. M. Claesen, Eric Verlind, Frank Proesmans, Hugo De Man
    Illustration of the SFG-Tracing Multi-Level Behavioral Verification Methodology, by the Correctness Proof of a High to Low Level Synthesis Application in CATHEDRAL-II. [Citation Graph (0, 0)][DBLP]
    ICCD, 1991, pp:338-341 [Conf]
  61. Eddy de Greef, Francky Catthoor, Hugo De Man
    Memory organization for video algorithms on programmable signal processors. [Citation Graph (0, 0)][DBLP]
    ICCD, 1995, pp:552-557 [Conf]
  62. Bill Lin, Hugo De Man
    Low-Power Driven Technology Mapping under Timing Constraints. [Citation Graph (0, 0)][DBLP]
    ICCD, 1993, pp:421-427 [Conf]
  63. Karl van Rompaey, Ivo Bolsens, Hugo De Man
    Just in Time Scheduling. [Citation Graph (0, 0)][DBLP]
    ICCD, 1992, pp:295-300 [Conf]
  64. Erik Brockmeyer, Francky Catthoor, Jan Bormans, Hugo De Man
    Code Transformations for Reduced Data Transfer and Storage in Low Power Realisations of MPEG-4 Full-Pel Motion Estimation. [Citation Graph (0, 0)][DBLP]
    ICIP (3), 1998, pp:985-989 [Conf]
  65. Aggeliki Prayati, Chun Wong, Paul Marchal, Nathalie Cossement, Francky Catthoor, Rudy Lauwereins, Diederik Verkest, Hugo De Man, Alexios N. Birbas
    Task Concurrency Management Experiment for Power-Efficient Speed-up of Embedded MPEG4 IM1 Player. [Citation Graph (0, 0)][DBLP]
    ICPP Workshops, 2000, pp:453-460 [Conf]
  66. P. Johannes, Luc J. M. Claesen, Hugo De Man
    Performance Through Hierarchy in Static Timing Verification. [Citation Graph (0, 0)][DBLP]
    IFIP Congress (1), 1992, pp:703-709 [Conf]
  67. Hugo De Man
    Behavioral Interactive Silicon Compilation for Real Time Synchronous Algorithms. [Citation Graph (0, 0)][DBLP]
    IFIP Congress, 1989, pp:380- [Conf]
  68. Diederik Verkest, Luc J. M. Claesen, Hugo De Man
    A Proof of the Non-Restoring Division Algorithm and its Implementation on the Cathedral-II ALU. [Citation Graph (0, 0)][DBLP]
    Designing Correct Circuits, 1992, pp:173-192 [Conf]
  69. Evagelos Katsadas, Z. Sahraoui, M. Wouters, Veerle Derudder, Ivo Bolsens, Paul Six, Hugo De Man
    Regular Module Generation or Standard Cells: Two Alternative Implementations of a Library of Functional Building Blocks. [Citation Graph (0, 0)][DBLP]
    Synthesis for Control Dominated Circuits, 1992, pp:167-181 [Conf]
  70. Augusli Kifli, R. De Wulf, J. Zegers, Gert Goossens, Paul Six, Hugo De Man
    Flag/Condition Handling and Branch Assignment for Large Microcoded Controllers. [Citation Graph (0, 0)][DBLP]
    Synthesis for Control Dominated Circuits, 1992, pp:61-71 [Conf]
  71. Chidamber Kulkarni, Francky Catthoor, Hugo De Man
    Advanced Data Layout Optimization for Multimedia Applications. [Citation Graph (0, 0)][DBLP]
    IPDPS Workshops, 2000, pp:186-193 [Conf]
  72. Chidamber Kulkarni, Francky Catthoor, Hugo De Man
    Code Transformations for Low Power Caching in Embedded Multimedia Processors. [Citation Graph (0, 0)][DBLP]
    IPPS/SPDP, 1998, pp:292-297 [Conf]
  73. Rudy J. van de Plassche, Bob Adams, Gerson A. S. Machado, Gabor C. Temes, Hugo De Man
    ASP 12: Forum - Analog Electronics - a European Speciality? [Citation Graph (0, 0)][DBLP]
    ISCAS, 1994, pp:705-710 [Conf]
  74. Jean-Philippe Diguet, Sven Wuytack, Francky Catthoor, Hugo De Man
    Formalized methodology for data reuse exploration in hierarchical memory mappings. [Citation Graph (0, 0)][DBLP]
    ISLPED, 1997, pp:30-35 [Conf]
  75. Kostas Masselos, Koen Danckaert, Francky Catthoor, Constantinos E. Goutis, Hugo De Man
    A methodology for power efficient partitioning of data-dominated algorithm specifications within performance constraints. [Citation Graph (0, 0)][DBLP]
    ISLPED, 1999, pp:270-272 [Conf]
  76. Giovanni De Micheli, Tony Correale, Pietro Erratico, Srini Raghvendra, Hugo De Man, Jerry Frankil, Vivek Tiwari
    Do our low-power tools have enough horse power? (panel session) (title only). [Citation Graph (0, 0)][DBLP]
    ISLPED, 2000, pp:149- [Conf]
  77. Julio Leao da Silva Jr., Francky Catthoor, Diederik Verkest, Hugo De Man
    Power exploration for dynamic data types through virtual memory management refinement. [Citation Graph (0, 0)][DBLP]
    ISLPED, 1998, pp:311-316 [Conf]
  78. Sven Wuytack, Francky Catthoor, Hugo De Man
    Transforming set data types to power optimal data structures. [Citation Graph (0, 0)][DBLP]
    ISLPD, 1995, pp:51-56 [Conf]
  79. Sven Wuytack, Francky Catthoor, Lode Nachtergaele, Hugo De Man
    Power exploration for data dominated video applications. [Citation Graph (0, 0)][DBLP]
    ISLPED, 1996, pp:359-364 [Conf]
  80. Miguel Miranda, Francky Catthoor, Martin Janssen, Hugo De Man
    ADOPT: Efficient Hardware Address Generation in Distributed Memory Architectures. [Citation Graph (0, 0)][DBLP]
    ISSS, 1996, pp:20-25 [Conf]
  81. Filip Thoen, Marco Cornero, Gert Goossens, Hugo De Man
    Real-time multi-tasking in software synthesis for information processing systems. [Citation Graph (0, 0)][DBLP]
    ISSS, 1995, pp:48-53 [Conf]
  82. H. Samsom, Frank H. M. Franssen, Francky Catthoor, Hugo De Man
    System level verification of video and image processing specifications. [Citation Graph (0, 0)][DBLP]
    ISSS, 1995, pp:144-149 [Conf]
  83. Patrick Schaumont, Bart Vanthournout, Ivo Bolsens, Hugo De Man
    Synthesis of pipelined DSP accelerators with dynamic scheduling. [Citation Graph (0, 0)][DBLP]
    ISSS, 1995, pp:72-77 [Conf]
  84. Sven Wuytack, Francky Catthoor, Gjalt G. de Jong, Bill Lin, Hugo De Man
    Flow Graph Balancing for Minimizing the Required Memory Bandwidth. [Citation Graph (0, 0)][DBLP]
    ISSS, 1996, pp:127-132 [Conf]
  85. Chantal Ykman-Couvreur, J. Lambrecht, Diederik Verkest, Francky Catthoor, Hugo De Man
    Exploration and Synthesis of Dynamic Data Sets in Telecom Network Applications. [Citation Graph (0, 0)][DBLP]
    ISSS, 1999, pp:85-93 [Conf]
  86. Jos van Sas, Francky Catthoor, Hugo De Man
    Optimized BIST Strategies for Programmable Data Paths Based on Cellular Automata. [Citation Graph (0, 0)][DBLP]
    ITC, 1992, pp:110-119 [Conf]
  87. Johannes Steensma, Francky Catthoor, Hugo De Man
    Partial Scan at the Register-Transfer Level. [Citation Graph (0, 0)][DBLP]
    ITC, 1993, pp:488-497 [Conf]
  88. Filip Thoen, Marco Cornero, Gert Goossens, Hugo De Man
    Software Synthesis for Real-Time Information Processing Systems. [Citation Graph (0, 0)][DBLP]
    Workshop on Languages, Compilers, & Tools for Real-Time Systems, 1995, pp:60-69 [Conf]
  89. Frederik Vermeulen, Lode Nachtergaele, Francky Catthoor, Diederik Verkest, Hugo De Man
    Flexible hardware acceleration for multimedia oriented microprocessors. [Citation Graph (0, 0)][DBLP]
    MICRO, 2000, pp:171-177 [Conf]
  90. Paul Marchal, Chun Wong, Aggeliki Prayati, Nathalie Cossement, Francky Catthoor, Rudy Lauwereins, Diederik Verkest, Hugo De Man
    Dynamic Memory Oriented Transformations in the MPEG4 IM1-Player on a Low Power Platform. [Citation Graph (0, 0)][DBLP]
    PACS, 2000, pp:40-50 [Conf]
  91. Hugo De Man
    Connecting E-Dreams to Deep-Submicron Realities. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2004, pp:1- [Conf]
  92. Koen Danckaert, Francky Catthoor, Hugo De Man
    Platform Independent Data Transfer and Storage Exploration Illustrated on Parallel Cavity Detection Algorithm. [Citation Graph (0, 0)][DBLP]
    PDPTA, 1999, pp:1669-1675 [Conf]
  93. Koen Danckaert, Francky Catthoor, Hugo De Man
    A loop transformation approach for combined parallelization and data transfer and storage optimization. [Citation Graph (0, 0)][DBLP]
    PDPTA, 2000, pp:- [Conf]
  94. Yajun Ha, Serge Vernalde, Patrick Schaumont, Marc Engels, Hugo De Man
    Building a Virtual Framework for Networked Reconfigurable Hardware and Software Objects. [Citation Graph (0, 0)][DBLP]
    PDPTA, 2000, pp:- [Conf]
  95. Yajun Ha, Patrick Schaumont, Marc Engels, Serge Vernalde, Freddy Potargent, Luc Rijnders, Hugo De Man
    A Hardware Virtual Machine for the Networked Reconfiguration. [Citation Graph (0, 0)][DBLP]
    IEEE International Workshop on Rapid System Prototyping, 2000, pp:194-199 [Conf]
  96. Antonis Papanikolaou, Miguel Miranda, Francky Catthoor, Henk Corporaal, Hugo De Man, David De Roest, Michele Stucchi, Karen Maex
    Global interconnect trade-off for technology over memory modules to application level: case study. [Citation Graph (0, 0)][DBLP]
    SLIP, 2003, pp:125-132 [Conf]
  97. Antonis Papanikolaou, Miguel Miranda, Francky Catthoor, Henk Corporaal, Hugo De Man, David De Roest, Michele Stucchi, Karen Maex
    Interconnect exploration for future wire dominated technologies. [Citation Graph (0, 0)][DBLP]
    SLIP, 2002, pp:105-106 [Conf]
  98. Diederik Verkest, J. Vandenbergh, Luc J. M. Claesen, Hugo De Man
    A Description Methodology for Parameterized Modules in the Boyer-Moore Logic. [Citation Graph (0, 0)][DBLP]
    TPCD, 1992, pp:37-57 [Conf]
  99. Catia M. Angelo, Luc J. M. Claesen, Hugo De Man
    The Formal Semantics Definition of a Multi-Rate DSP Specification Language in HOL. [Citation Graph (0, 0)][DBLP]
    TPHOLs, 1992, pp:375-394 [Conf]
  100. Catia M. Angelo, Luc J. M. Claesen, Hugo De Man
    Degrees of Formality in Shallow Embedding Hardware Description Languages in HOL. [Citation Graph (0, 0)][DBLP]
    HUG, 1993, pp:89-100 [Conf]
  101. Catia M. Angelo, Luc J. M. Claesen, Hugo De Man
    Reasoning About a Class of Linear Systems of Equations in HOL. [Citation Graph (0, 0)][DBLP]
    TPHOLs, 1994, pp:33-48 [Conf]
  102. Catia M. Angelo, Diederik Verkest, Luc J. M. Claesen, Hugo De Man
    Formal Hardware Verification in HOL and in Boyer-Moore: A Comparative Analysis. [Citation Graph (0, 0)][DBLP]
    TPHOLs, 1991, pp:340-347 [Conf]
  103. W. Ploegaerts, Luc J. M. Claesen, Hugo De Man
    Defining Recursive Functions in HOL. [Citation Graph (0, 0)][DBLP]
    TPHOLs, 1991, pp:358-366 [Conf]
  104. Werner Geurts, Stefaan Note, Francky Catthoor, Hugo De Man
    Partitioning-Based Allocation of Dedicated Data-Paths in the Architectural Synthesis for High Throughput Applications. [Citation Graph (0, 0)][DBLP]
    VLSI, 1991, pp:193-202 [Conf]
  105. Hugo De Man
    Invited Address: Future Systems-on-a-Chip: Impact on Engineering Education. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1998, pp:572-577 [Conf]
  106. Koen Danckaert, Chidamber Kulkarni, Francky Catthoor, Hugo De Man, Vivek Tiwari
    A Systematic Approach for System Bus Load Reduction Applied to Medical Imaging. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2001, pp:48-0 [Conf]
  107. S. Samel, Bert Gyselinckx, Ivo Bolsens, Hugo De Man
    Designing Systems On Silicon: A Digital Spread Spectrum Pager. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1996, pp:311-312 [Conf]
  108. Hugo De Man
    Design Technology Research and Education for Deep-Submicron Systems of the Next Century. [Citation Graph (0, 0)][DBLP]
    VTS, 1999, pp:8-15 [Conf]
  109. Hugo De Man
    Submicron design tools: problems and suppliers. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 1996, v:13, n:2, pp:4- [Journal]
  110. Hugo De Man
    System-on-Chip Design: Impact on Education and Research. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 1999, v:16, n:3, pp:11-19 [Journal]
  111. Miroslav Cupák, Francky Catthoor, Hugo De Man
    Efficient System-Level Functional Verification Methodology for Multimedia Applications. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2003, v:20, n:2, pp:56-64 [Journal]
  112. Jos van Sas, Francky Catthoor, Hugo De Man
    Test Algorithms for Double-Buffered Random Access and Pointer-Addressed Memories. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 1993, v:10, n:2, pp:34-44 [Journal]
  113. Catia M. Angelo, Luc J. M. Claesen, Hugo De Man
    Modeling Multi-rate DSP Specification Semantics for Formal Transformational Design in HOL. [Citation Graph (0, 0)][DBLP]
    Formal Methods in System Design, 1994, v:5, n:1/2, pp:61-94 [Journal]
  114. Catia M. Angelo, Diederik Verkest, Luc J. M. Claesen, Hugo De Man
    On the Comparison of HOL and Boyer-Moore for Formal Hardware Verification. [Citation Graph (0, 0)][DBLP]
    Formal Methods in System Design, 1993, v:2, n:1, pp:45-72 [Journal]
  115. Diederik Verkest, Luc J. M. Claesen, Hugo De Man
    A Proof of the Nonrestoring Division Algorithm and its Implementation on an ALU. [Citation Graph (0, 0)][DBLP]
    Formal Methods in System Design, 1994, v:4, n:1, pp:5-31 [Journal]
  116. Hugo De Man
    Entwurf von Nanosystemen für Ambient Intelligence. [Citation Graph (0, 0)][DBLP]
    it - Information Technology, 2003, v:45, n:6, pp:- [Journal]
  117. Chen-Yi Lee, Francky Catthoor, Hugo De Man
    Efficient VLSI Architectures for a High-Performance Digital Image Communication System. [Citation Graph (0, 0)][DBLP]
    IEEE Journal on Selected Areas in Communications, 1990, v:8, n:8, pp:1481-1491 [Journal]
  118. Eddy de Greef, Francky Catthoor, Hugo De Man
    Memory Size Reduction Through Storage Order Optimization for Embedded Parallel Multimedia Applications. [Citation Graph (0, 0)][DBLP]
    Parallel Computing, 1997, v:23, n:12, pp:1811-1837 [Journal]
  119. M. F. X. B. van Swaaij, Francky Catthoor, Hugo De Man
    Deriving ASIC architectures for the Hough transform. [Citation Graph (0, 0)][DBLP]
    Parallel Computing, 1990, v:16, n:1, pp:113-121 [Journal]
  120. Florin Balasa, Frank H. M. Franssen, Francky Catthoor, Hugo De Man
    Transformation of Nested Loops with Modulo Indexing to Affine Recurrences. [Citation Graph (0, 0)][DBLP]
    Parallel Processing Letters, 1994, v:4, n:, pp:271-280 [Journal]
  121. Chidamber Kulkarni, C. Ghez, Miguel Miranda, Francky Catthoor, Hugo De Man
    Cache Conscious Data Layout Organization for Conflict Miss Reduction in Embedded Multimedia Applications. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2005, v:54, n:1, pp:76-81 [Journal]
  122. Mustafa Badaroglu, Kris Tiri, Geert Van der Plas, Piet Wambacq, Ingrid Verbauwhede, Stéphane Donnay, Georges G. E. Gielen, Hugo De Man
    Clock-skew-optimization methodology for substrate-noise reduction with supply-current folding. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:6, pp:1146-1154 [Journal]
  123. Mustafa Badaroglu, Piet Wambacq, Geert Van der Plas, Stéphane Donnay, Georges G. E. Gielen, Hugo De Man
    Digital ground bounce reduction by supply current shaping and clock frequency Modulation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:1, pp:65-76 [Journal]
  124. Florin Balasa, Francky Catthoor, Hugo De Man
    Practical solutions for counting scalars and dependences in ATOMIUM-a memory management system for multidimensional signal processing. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1997, v:16, n:2, pp:133-145 [Journal]
  125. Jacques Benkoski, E. Vanden Meersch, Luc J. M. Claesen, Hugo De Man
    Timing verification using statically sensitizable paths. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1990, v:9, n:10, pp:10723-10784 [Journal]
  126. Dundar Dumlugol, Hugo De Man, Piet Stevens, Guido G. Schrooten
    Local Relaxation Algorithms for Event-Driven Simulation of MOS Networks Including Assignable Delay Modeling. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1983, v:2, n:3, pp:193-202 [Journal]
  127. Dundar Dumlugol, Patrick Odent, Johan Cockx, Hugo De Man
    Switch-Electrical Segmented Waveform Relaxation for Digital MOS VLSI and Its Acceleration on Parallel Computers. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1987, v:6, n:6, pp:992-1005 [Journal]
  128. Werner Geurts, Francky Catthoor, Hugo De Man
    Quadratic zero-one programming-based synthesis of application-specific data paths. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1995, v:14, n:1, pp:1-11 [Journal]
  129. Gert Goossens, Jan M. Rabaey, Joos Vandewalle, Hugo De Man
    An efficient microcode compiler for application specific DSP processors. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1990, v:9, n:9, pp:925-937 [Journal]
  130. Manuel Innocent, Piet Wambacq, Stéphane Donnay, Harrie A. C. Tilmans, Willy M. C. Sansen, Hugo De Man
    An analytic Volterra-series-based model for a MEMS variable capacitor. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:2, pp:124-131 [Journal]
  131. Hugo De Man, Ivo Bolsens, E. Vanden Meersch, Johan Van Cleynenbreugel
    DIALOG: An Expert Debugging System for MOSVLSI Design. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1985, v:4, n:3, pp:303-311 [Journal]
  132. Stefaan Note, Francky Catthoor, Gert Goossens, Hugo De Man
    Combined hardware selection and pipelining in high-performance data-path design. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1992, v:11, n:4, pp:413-423 [Journal]
  133. Patrick Odent, Luc J. M. Claesen, Hugo De Man
    Acceleration of relaxation-based circuit simulation using a multiprocessor system. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1990, v:9, n:10, pp:1063-1072 [Journal]
  134. Jos van Sas, Francky Catthoor, Hugo De Man
    Cellular automata based deterministic self-test strategies for programmable data paths. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1994, v:13, n:7, pp:940-949 [Journal]
  135. Peter Vanbekbergen, Gert Goossens, Francky Catthoor, Hugo De Man
    Optimized synthesis of asynchronous control circuits from graph-theoretic specifications. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1992, v:11, n:11, pp:1426-1438 [Journal]
  136. I. Vandeweerd, Kris Croes, Luc Rijnders, Paul Six, Hugo De Man
    REDUSA: module generation by automatic elimination of superfluous blocks in regular structures. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1989, v:8, n:9, pp:989-998 [Journal]
  137. Paul Vanoostende, Paul Six, Hugo De Man
    DARSI: RC data reduction [VLSI simulation]. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1991, v:10, n:4, pp:493-500 [Journal]
  138. Sven Wuytack, Francky Catthoor, Hugo De Man
    Transforming set data types to power optimal data structures. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1996, v:15, n:6, pp:619-629 [Journal]
  139. Chantal Ykman-Couvreur, J. Lambrecht, A. Van Der Togt, Francky Catthoor, Hugo De Man
    System-level exploration of association table implementations in telecom network applications. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Embedded Comput. Syst., 2002, v:1, n:1, pp:106-140 [Journal]
  140. Yajun Ha, Serge Vernalde, Patrick Schaumont, Marc Engels, Rudy Lauwereins, Hugo De Man
    Building a Virtual Framework for Networked Reconfigurable Hardware and Software Objects. [Citation Graph (0, 0)][DBLP]
    The Journal of Supercomputing, 2002, v:21, n:2, pp:131-144 [Journal]
  141. Erik Brockmeyer, Lode Nachtergaele, Francky Catthoor, Jan Bormans, Hugo De Man
    Low Power Memory Storage and Transfer Organization for the MPEG-4 Full Pel Motion Estimation on a Multimedia Processor. [Citation Graph (0, 0)][DBLP]
    IEEE Transactions on Multimedia, 1999, v:1, n:2, pp:202-216 [Journal]
  142. Mustafa Badaroglu, Geert Van der Plas, Piet Wambacq, Stéphane Donnay, Georges G. E. Gielen, Hugo De Man
    SWAN: high-level simulation methodology for digital substrate noise generation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2006, v:14, n:1, pp:23-33 [Journal]
  143. Mustafa Badaroglu, Geert Van der Plas, Piet Wambacq, Stéphane Donnay, Georges G. E. Gielen, Hugo De Man
    Scalable Gate-Level Models for Power and Timing Analysis. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:2938-2941 [Conf]
  144. Geert Van Meerbergen, Marc Moonen, Hugo De Man
    Reed-Solomon Codes Implementing a Coded OFDM Scheme for Rayleigh Fading Channels. [Citation Graph (0, 0)][DBLP]
    GLOBECOM, 2006, pp:- [Conf]
  145. Frank H. M. Franssen, Florin Balasa, M. F. X. B. van Swaaij, Francky Catthoor, Hugo De Man
    Modeling multidimensional data and control flow. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1993, v:1, n:3, pp:319-327 [Journal]
  146. Florin Balasa, Francky Catthoor, Hugo De Man
    Background memory area estimation for multidimensional signal processing systems. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1995, v:3, n:2, pp:157-172 [Journal]
  147. Patrick Schaumont, Bart Vanthournout, Ivo Bolsens, Hugo De Man
    Synthesis of pipelined DSP accelerators with dynamic scheduling. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1997, v:5, n:1, pp:59-68 [Journal]
  148. Sven Wuytack, Jean-Philippe Diguet, F. V. M. Catthoor, Hugo De Man
    Formalized methodology for data reuse: exploration for low-power hierarchical memory mappings. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1998, v:6, n:4, pp:529-537 [Journal]
  149. Miguel Miranda, Francky Catthoor, Martin Janssen, Hugo De Man
    High-level address optimization and synthesis techniques for data-transfer-intensive applications. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1998, v:6, n:4, pp:677-686 [Journal]
  150. Gauthier Lafruit, Francky Catthoor, Jan Cornelis, Hugo De Man
    An efficient VLSI architecture for 2-D wavelet image coding with novel image scan. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1999, v:7, n:1, pp:56-68 [Journal]
  151. Koen Danckaert, Kostas Masselos, Francky Catthoor, Hugo De Man, Constantinos E. Goutis
    Strategy for power-efficient design of parallel systems. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1999, v:7, n:2, pp:258-265 [Journal]
  152. Sven Wuytack, Francky Catthoor, Gjalt G. de Jong, Hugo De Man
    Minimizing the required memory bandwidth in VLSI system realizations. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1999, v:7, n:4, pp:433-441 [Journal]
  153. Frederik Vermeulen, Francky Catthoor, Diederik Verkest, Hugo De Man
    Formalized three-layer system-level model and reuse methodology for embedded data-dominated applications. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2000, v:8, n:2, pp:207-216 [Journal]
  154. Kostas Masselos, Francky Catthoor, Constantinos E. Goutis, Hugo De Man
    A systematic methodology for the application of data transfer and storage optimizing code transformations for power consumption and execution time reduction in realizations of multimedia algorithms on programmable processors. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2002, v:10, n:4, pp:515-518 [Journal]
  155. Frederik Vermeulen, Francky Catthoor, Lode Nachtergaele, Diederik Verkest, Hugo De Man
    Power-efficient flexible processor architecture for embedded applications. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2003, v:11, n:3, pp:376-385 [Journal]

  156. Architectural exploration and optimization for counter based hardware address generation. [Citation Graph (, )][DBLP]


  157. Multi-thread graph: a system model for real-time embedded software synthesis. [Citation Graph (, )][DBLP]


  158. Timing optimization by bit-level arithmetic transformations. [Citation Graph (, )][DBLP]


  159. Search space reduction through clustering in test generation. [Citation Graph (, )][DBLP]


  160. SPI: an open interface integrating highly interactive electronic CAD tools. [Citation Graph (, )][DBLP]


  161. A combined waveform relaxation: waveform relaxation newton algorithm for efficient parallel circuit simulation. [Citation Graph (, )][DBLP]


  162. SLOCOP-II: a versatile timing verification system for MOSVLSI. [Citation Graph (, )][DBLP]


  163. Correctness proofs of parameterized hardware modules in the CATHEDRAL-II synthesis environment. [Citation Graph (, )][DBLP]


  164. Open-ended system for high-level synthesis of flexible signal processors. [Citation Graph (, )][DBLP]


  165. CGE: automatic generation of controllers in the CATHEDRAL-II silicon compiler. [Citation Graph (, )][DBLP]


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