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## Search the dblp DataBase
Weijia Shang:
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## Publications of Author- Edin Hodzic, Weijia Shang
**On Supernode Transformation with Minimized Total Running Time.**[Citation Graph (0, 0)][DBLP] ASAP, 1996, pp:402-414 [Conf] - Weijia Shang, Matthew T. O'Keefe, José A. B. Fortes
**Generalized cycle shrinking.**[Citation Graph (0, 0)][DBLP] Algorithms and Parallel VLSI Architectures, 1991, pp:131-144 [Conf] - Radhika S. Grover, Weijia Shang, Qiang Li
**A faster distributed arithmetic architecture for FPGAs.**[Citation Graph (0, 0)][DBLP] FPGA, 2002, pp:31-39 [Conf] - Radhika S. Grover, Weijia Shang, Qiang Li
**A Comparison of FPGA Implementations of Bit-Level and Word-Level Matrix Multipliers.**[Citation Graph (0, 0)][DBLP] FPL, 2000, pp:422-431 [Conf] - Edin Hodzic, Weijia Shang
**On Optimal Size and Shape of Supernode Transformations.**[Citation Graph (0, 0)][DBLP] ICPP, Vol. 3, 1996, pp:25-34 [Conf] - Weijia Shang, José A. B. Fortes
**Independent Partitioning of Algorithms With Uniform Data Dependencies.**[Citation Graph (0, 0)][DBLP] ICPP (2), 1988, pp:26-33 [Conf] - Weijia Shang, José A. B. Fortes
**Time-Optimal and Conflict-Free Mappings of Uniform Dependence Algorithms into Lower Dimensional Processor Arrays.**[Citation Graph (0, 0)][DBLP] ICPP (1), 1990, pp:101-110 [Conf] - Weijia Shang, Matthew T. O'Keefe, José A. B. Fortes
**On Loop Transformations for Generalized Cycle Shrinking.**[Citation Graph (0, 0)][DBLP] ICPP (2), 1991, pp:132-141 [Conf] - Weijia Shang, Benjamin W. Wah
**Dependence Analysis and Architecture Design for Bit-Level Algorithms.**[Citation Graph (0, 0)][DBLP] ICPP, 1993, pp:30-38 [Conf] - Margaret A. Schaar, Kemal Efe, Weijia Shang
**Queueing performance analysis of co-scheduling in a pool of processors environment.**[Citation Graph (0, 0)][DBLP] International Conference on Supercomputing, 1994, pp:313-322 [Conf] - Zhigang Chen, Weijia Shang
**Mapping of Uniform Dependence Algorithm onto Fixed Size Processor Arrays.**[Citation Graph (0, 0)][DBLP] IPPS, 1993, pp:804-809 [Conf] - Zhenhui Yang, Weijia Shang, José A. B. Fortes
**Conflict-Free Scheduling of Nested Loop Algorithms on Lower Dimensional Processor Arrays.**[Citation Graph (0, 0)][DBLP] IPPS, 1992, pp:156-164 [Conf] - Radhika S. Grover, Shobha Krishnan, Weijia Shang, Qiang Li
**Performance Trade-offs of DCT with Variable Length Carry Chains in FPGAs.**[Citation Graph (0, 0)][DBLP] PDPTA, 2004, pp:442-448 [Conf] - Edin Hodzic, Weijia Shang
**On Time Optimal Supernode Shape.**[Citation Graph (0, 0)][DBLP] PDPTA, 1999, pp:2019-2026 [Conf] - Srinivasan Subha, Weijia Shang
**On Data Locality in Supernode Transformation.**[Citation Graph (0, 0)][DBLP] PDPTA, 2003, pp:1635-1641 [Conf] - Zhigang Chen, Weijia Shang
**On Uniformization of Affine Dependence Algorithms.**[Citation Graph (0, 0)][DBLP] SPDP, 1992, pp:128-137 [Conf] - José A. B. Fortes, Benjamin W. Wah, Weijia Shang, Kumar N. Ganapathy
**Algorithm-Specific Parallel Processing with Linear Processor Arrays.**[Citation Graph (0, 0)][DBLP] Advances in Computers, 1994, v:38, n:, pp:197-245 [Journal] - Radhika S. Grover, Weijia Shang, Qiang Li
**Bit-level two's complement matrix multiplication.**[Citation Graph (0, 0)][DBLP] Integration, 2002, v:33, n:1-2, pp:3-21 [Journal] - Benjamin W. Wah, Mokhtar Aboelaze, Weijia Shang
**Systematic Designs of Buffers in Macropipelines of Systolic Arrays.**[Citation Graph (0, 0)][DBLP] J. Parallel Distrib. Comput., 1988, v:5, n:1, pp:1-25 [Journal] - Weijia Shang, José A. B. Fortes
**Time Optimal Linear Schedules for Algorithms with Uniform Dependencies.**[Citation Graph (0, 0)][DBLP] IEEE Trans. Computers, 1991, v:40, n:6, pp:723-742 [Journal] - Weijia Shang, José A. B. Fortes
**Independent Partitioning of Algorithms with Uniform Dependencies.**[Citation Graph (0, 0)][DBLP] IEEE Trans. Computers, 1992, v:41, n:2, pp:190-206 [Journal] - Weijia Shang, Edin Hodzic, Zhigang Chen
**On Uniformization of Affine Dependence Algorithms.**[Citation Graph (0, 0)][DBLP] IEEE Trans. Computers, 1996, v:45, n:7, pp:827-840 [Journal] - Edin Hodzic, Weijia Shang
**On Time Optimal Supernode Shape.**[Citation Graph (0, 0)][DBLP] IEEE Trans. Parallel Distrib. Syst., 2002, v:13, n:12, pp:1220-1233 [Journal] - Edin Hodzic, Weijia Shang
**On Supernode Transformation with Minimized Total Running Time.**[Citation Graph (0, 0)][DBLP] IEEE Trans. Parallel Distrib. Syst., 1998, v:9, n:5, pp:417-428 [Journal] - Weijia Shang, José A. B. Fortes
**On Time Mapping of Uniform Dependence Algorithms into Lower Dimensional Processor Arrays.**[Citation Graph (0, 0)][DBLP] IEEE Trans. Parallel Distrib. Syst., 1992, v:3, n:3, pp:350-363 [Journal] - Weijia Shang, Matthew T. O'Keefe, José A. B. Fortes
**On Loop Transformations for Generalized Cycle Shrinking.**[Citation Graph (0, 0)][DBLP] IEEE Trans. Parallel Distrib. Syst., 1994, v:5, n:2, pp:193-204 [Journal] - Stefan Schäckeler, Weijia Shang
**Stack size reduction of recursive programs.**[Citation Graph (0, 0)][DBLP] CASES, 2007, pp:48-52 [Conf] - Jun Zhang, Xiaoquan Yi, Nam Ling, Weijia Shang
**Chroma Coding Efficiency Improvement with Context Adaptive Lagrange Multiplier (CALM).**[Citation Graph (0, 0)][DBLP] ISCAS, 2007, pp:293-296 [Conf] **Procedural Abstraction with Reverse Prefix Trees.**[Citation Graph (, )][DBLP]**Optimal dissemination of layered videos in P2P-Based IPTV networks.**[Citation Graph (, )][DBLP]**Coefficient Conversion for Transform Domain VC-1 TO H.264 Transcoding.**[Citation Graph (, )][DBLP]**Optimizing the stack size of recursive functions.**[Citation Graph (, )][DBLP]**On minimizing register usage of linearly scheduled algorithms with uniform dependencies.**[Citation Graph (, )][DBLP]**Visualization of Procedural Abstraction.**[Citation Graph (, )][DBLP]
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