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Heinrich Meyr: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Jens Horstmannshoff, Thorsten Grötker, Heinrich Meyr
    Mapping multirate dataflow to complex RT level hardware models. [Citation Graph (0, 0)][DBLP]
    ASAP, 1997, pp:283-0 [Conf]
  2. Stefan Pees, Martin Vaupel, Vojin Zivojnovic, Heinrich Meyr
    On core and more: a design perspective for systems-on-a-chip. [Citation Graph (0, 0)][DBLP]
    ASAP, 1997, pp:448-457 [Conf]
  3. Md. Mostafizur Rahman Mozumdar, Kingshuk Karuri, Anupam Chattopadhyay, Stefan Kraemer, Hanno Scharwächter, Heinrich Meyr, Gerd Ascheid, Rainer Leupers
    Instruction Set Customization of Application Specific Processors for Network Processing: A Case Study. [Citation Graph (0, 0)][DBLP]
    ASAP, 2005, pp:154-160 [Conf]
  4. Oliver Schliebusch, Anupam Chattopadhyay, David Kammler, Gerd Ascheid, Rainer Leupers, Heinrich Meyr, Tim Kogel
    A framework for automated and optimized ASIP implementation supporting multiple hardware description languages. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2005, pp:280-285 [Conf]
  5. Oliver Schliebusch, Andreas Hoffmann, Achim Nohl, Gunnar Braun, Heinrich Meyr
    Architecture Implementation Using the Machine Description Language LISA. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2002, pp:239-244 [Conf]
  6. Tim Kogel, Malte Doerper, Andreas Wieferink, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, Serge Goossens
    A modular simulation framework for architectural exploration of on-chip interconnection networks. [Citation Graph (0, 0)][DBLP]
    CODES+ISSS, 2003, pp:7-12 [Conf]
  7. Andreas Wieferink, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, Tom Michiels, Achim Nohl, Tim Kogel
    Retargetable generation of TLM bus interfaces for MP-SoC platforms. [Citation Graph (0, 0)][DBLP]
    CODES+ISSS, 2005, pp:249-254 [Conf]
  8. Manuel Hohenauer, Christoph Schumacher, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, Hans van Someren
    Retargetable code optimization with SIMD instructions. [Citation Graph (0, 0)][DBLP]
    CODES+ISSS, 2006, pp:148-153 [Conf]
  9. Gunnar Braun, Achim Nohl, Weihua Sheng, Jianjiang Ceng, Manuel Hohenauer, Hanno Scharwächter, Rainer Leupers, Heinrich Meyr
    A novel approach for flexible and consistent ADL-driven ASIP design. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:717-722 [Conf]
  10. Jens Horstmannshoff, Heinrich Meyr
    Efficient building block based RTL code generation from synchronous data flow graphs. [Citation Graph (0, 0)][DBLP]
    DAC, 2000, pp:552-555 [Conf]
  11. Kingshuk Karuri, Mohammad Abdullah Al Faruque, Stefan Kraemer, Rainer Leupers, Gerd Ascheid, Heinrich Meyr
    Fine-grained application source code profiling for ASIP design. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:329-334 [Conf]
  12. Holger Keding, Martin Coors, Olaf Lüthje, Heinrich Meyr
    Fast Bit-True Simulation. [Citation Graph (0, 0)][DBLP]
    DAC, 2001, pp:708-713 [Conf]
  13. Tim Kogel, Heinrich Meyr
    Heterogeneous MP-SoC: the solution to energy-efficient signal processing. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:686-691 [Conf]
  14. Achim Nohl, Gunnar Braun, Oliver Schliebusch, Rainer Leupers, Heinrich Meyr, Andreas Hoffmann
    A universal technique for fast and flexible instruction-set architecture simulation. [Citation Graph (0, 0)][DBLP]
    DAC, 2002, pp:22-27 [Conf]
  15. Achim Nohl, Volker Greive, Gunnar Braun, Andreas Hoffmann, Rainer Leupers, Oliver Schliebusch, Heinrich Meyr
    Instruction encoding synthesis for architecture exploration using hierarchical processor models. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:262-267 [Conf]
  16. Stefan Pees, Andreas Hoffmann, Vojin Zivojnovic, Heinrich Meyr
    LISA - Machine Description Language for Cycle-Accurate Models of Programmable DSP Architectures. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:933-938 [Conf]
  17. Markus Willems, Volker Bürsgens, Holger Keding, Thorsten Grötker, Heinrich Meyr
    System Level Fixed-Point Design Based on an Interpolative Approach. [Citation Graph (0, 0)][DBLP]
    DAC, 1997, pp:293-298 [Conf]
  18. Vojin Zivojnovic, Heinrich Meyr
    Compiled HW/SW Co-Simulation. [Citation Graph (0, 0)][DBLP]
    DAC, 1996, pp:690-695 [Conf]
  19. Peter Zepter, Thorsten Grötker, Heinrich Meyr
    Digital Receiver Design Using VHDL Generation from Data Flow Graphs. [Citation Graph (0, 0)][DBLP]
    DAC, 1995, pp:228-233 [Conf]
  20. Gunnar Braun, Andreas Wieferink, Oliver Schliebusch, Rainer Leupers, Heinrich Meyr, Achim Nohl
    Processor/Memory Co-Exploration on Multiple Abstraction Levels. [Citation Graph (0, 0)][DBLP]
    DATE, 2003, pp:10966-10973 [Conf]
  21. Jianjiang Ceng, Manuel Hohenauer, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, Gunnar Braun
    C Compiler Retargeting Based on Instruction Semantics Models. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:1150-1155 [Conf]
  22. Anupam Chattopadhyay, B. Geukes, David Kammler, Ernst Martin Witte, Oliver Schliebusch, H. Ishebabi, Rainer Leupers, Gerd Ascheid, Heinrich Meyr
    Automatic ADL-based operand isolation for embedded processors. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:600-605 [Conf]
  23. Luca Fanucci, Michele Cassiano, Sergio Saponara, David Kammler, Ernst Martin Witte, Oliver Schliebusch, Gerd Ascheid, Rainer Leupers, Heinrich Meyr
    ASIP design and synthesis for non linear filtering in image processing. [Citation Graph (0, 0)][DBLP]
    DATE Designers' Forum, 2006, pp:233-238 [Conf]
  24. Andreas Hoffmann, Tim Kogel, Heinrich Meyr
    A framework for fast hardware-software co-simulation. [Citation Graph (0, 0)][DBLP]
    DATE, 2001, pp:760-765 [Conf]
  25. Andreas Hoffmann, Achim Nohl, Stefan Pees, Gunnar Braun, Heinrich Meyr
    Generating production quality software development tools using a machine description language. [Citation Graph (0, 0)][DBLP]
    DATE, 2001, pp:674-678 [Conf]
  26. Manuel Hohenauer, Hanno Scharwächter, Kingshuk Karuri, Oliver Wahlen, Tim Kogel, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, Gunnar Braun, Hans van Someren
    A Methodology and Tool Suite for C Compiler Generation from ADL Processor Models. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:1276-1283 [Conf]
  27. Kingshuk Karuri, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, Monu Kedia
    Design and implementation of a modular and portable IEEE 754 compliant floating-point unit. [Citation Graph (0, 0)][DBLP]
    DATE Designers' Forum, 2006, pp:221-226 [Conf]
  28. Holger Keding, Markus Willems, Martin Coors, Heinrich Meyr
    FRIDGE: A Fixed-Point Design and Simulation Environment. [Citation Graph (0, 0)][DBLP]
    DATE, 1998, pp:429-435 [Conf]
  29. Torsten Kempf, Malte Doerper, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, Tim Kogel, Bart Vanthournout
    A Modular Simulation Framework for Spatial and Temporal Task Mapping onto Multi-Processor SoC Platforms. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:876-881 [Conf]
  30. Torsten Kempf, Kingshuk Karuri, Stefan Wallentowitz, Gerd Ascheid, Rainer Leupers, Heinrich Meyr
    A SW performance estimation framework for early system-level-design using fine-grained instrumentation. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:468-473 [Conf]
  31. A. Lock, Raul Camposano, Heinrich Meyr
    The programmable platform: does one size fit all? [Citation Graph (0, 0)][DBLP]
    DATE, 2001, pp:226-227 [Conf]
  32. Stefan Pees, Andreas Hoffmann, Heinrich Meyr
    Retargeting of Compiled Simulators for Digital Signal Processors Using a Machine Description Language. [Citation Graph (0, 0)][DBLP]
    DATE, 2000, pp:669-673 [Conf]
  33. Hanno Scharwächter, Manuel Hohenauer, Rainer Leupers, Gerd Ascheid, Heinrich Meyr
    An interprocedural code optimization technique for network processors using hardware multi-threading support. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:919-924 [Conf]
  34. Oliver Schliebusch, Anupam Chattopadhyay, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, Mario Steinert, Gunnar Braun, Achim Nohl
    RTL Processor Synthesis for Architecture Exploration and Implementation. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:156-160 [Conf]
  35. Andreas Wieferink, Tim Kogel, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, Gunnar Braun, Achim Nohl
    A System Level Processor/Communication Co-Exploration Methodology for Multi-Processor System-on-Chip Platform. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:1256-1263 [Conf]
  36. Kingshuk Karuri, Christian Huben, Rainer Leupers, Gerd Ascheid, Heinrich Meyr
    Memory Access Micro-Profiling for ASIP Design. [Citation Graph (0, 0)][DBLP]
    DELTA, 2006, pp:255-262 [Conf]
  37. Michael Speth, Alexander Jansen, Heinrich Meyr
    Iterative Multiuser Detection for Bit Interleaved Coed Modulation. [Citation Graph (0, 0)][DBLP]
    ICC (2), 2000, pp:894-898 [Conf]
  38. Andreas Hoffmann, Oliver Schliebusch, Achim Nohl, Gunnar Braun, Oliver Wahlen, Heinrich Meyr
    A Methodology for the Design of Application Specific Instruction Set Processors (ASIP) using the Machine Description Language LISA. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2001, pp:625-630 [Conf]
  39. K. ten Hagen, Heinrich Meyr
    Partitioning and Surmounting the Software-Hardware Abstraction Gap in an ASIC Design Project. [Citation Graph (0, 0)][DBLP]
    ICCD, 1993, pp:462-465 [Conf]
  40. Francky Catthoor, Ed F. Deprettere, Yu Hen Hu, Jan M. Rabaey, Heinrich Meyr, Lothar Thiele
    Is it Possible to achieve a Teraflop/s on a chip? From High Performance Algorithms to Architectures. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1994, pp:129-136 [Conf]
  41. Martin Vaupel, Heinrich Meyr
    High Speed FIR-Filter Architectures with Scalable Sample Rates. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1994, pp:127-130 [Conf]
  42. Vojin Zivojnovic, Heinrich Meyr
    Design of optimum interpolation filters for digital demodulators. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1993, pp:140-143 [Conf]
  43. Tobias Noll, Heinrich Meyr
    Designing SoC's. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2002, pp:283- [Conf]
  44. Peter Wintermayr, Reiner W. Hartenstein, Heinrich Meyr, Steve Leibson
    Flexibility and low power: a contradiction in terms? [Citation Graph (0, 0)][DBLP]
    ISLPED, 2006, pp:375- [Conf]
  45. Jens Horstmannshoff, Heinrich Meyr
    Optimized System Synthesis of Complex RT Level Building Blocks from Multirate Dataflow Graphs. [Citation Graph (0, 0)][DBLP]
    ISSS, 1999, pp:38-43 [Conf]
  46. Gunnar Braun, Andreas Hoffmann, Achim Nohl, Heinrich Meyr
    Using static scheduling techniques for the retargeting of high speed, compiled simulators for embedded processors from an abstract machine description. [Citation Graph (0, 0)][DBLP]
    ISSS, 2001, pp:57-62 [Conf]
  47. Vojin Zivojnovic, Stefan Pees, C. Schälger, Markus Willems, R. Schoenen, Heinrich Meyr
    DSP Processor/Compiler Co-Design: A Quantitative Approach. [Citation Graph (0, 0)][DBLP]
    ISSS, 1996, pp:108-0 [Conf]
  48. Claus Schotten, Heinrich Meyr
    Test Point Insertion for an Area Efficient BIST. [Citation Graph (0, 0)][DBLP]
    ITC, 1995, pp:515-523 [Conf]
  49. Oliver Wahlen, Tilman Glökler, Achim Nohl, Andreas Hoffmann, Rainer Leupers, Heinrich Meyr
    Application specific compiler/architecture codesign: a case study. [Citation Graph (0, 0)][DBLP]
    LCTES-SCOPES, 2002, pp:185-193 [Conf]
  50. Anupam Chattopadhyay, Arnab Sinha, Diandian Zhang, Rainer Leupers, Gerd Ascheid, Heinrich Meyr
    Integrated Verification Approach during ADL-Driven Processor Design. [Citation Graph (0, 0)][DBLP]
    IEEE International Workshop on Rapid System Prototyping, 2006, pp:110-118 [Conf]
  51. Oliver Schliebusch, Anupam Chattopadhyay, Ernst Martin Witte, David Kammler, Gerd Ascheid, Rainer Leupers, Heinrich Meyr
    Optimization Techniques for ADL-Driven RTL Processor Synthesis. [Citation Graph (0, 0)][DBLP]
    IEEE International Workshop on Rapid System Prototyping, 2005, pp:165-171 [Conf]
  52. Tim Kogel, Malte Doerper, Torsten Kempf, Andreas Wieferink, Rainer Leupers, Gerd Ascheid, Heinrich Meyr
    Virtual Architecture Mapping: A SystemC Based Methodology for Architectural Exploration of System-on-Chip Designs. [Citation Graph (0, 0)][DBLP]
    SAMOS, 2004, pp:138-148 [Conf]
  53. Jianjiang Ceng, Weihua Sheng, Manuel Hohenauer, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, Gunnar Braun
    Modeling Instruction Semantics in ADL Processor Descriptions for C Compiler Retargeting. [Citation Graph (0, 0)][DBLP]
    SAMOS, 2004, pp:463-473 [Conf]
  54. Andreas Wieferink, Malte Doerper, Tim Kogel, Rainer Leupers, Gerd Ascheid, Heinrich Meyr
    Early ISS Integration into Network-on-Chip Designs. [Citation Graph (0, 0)][DBLP]
    SAMOS, 2004, pp:443-452 [Conf]
  55. Hanno Scharwächter, David Kammler, Andreas Wieferink, Manuel Hohenauer, Kingshuk Karuri, Jianjiang Ceng, Rainer Leupers, Gerd Ascheid, Heinrich Meyr
    ASIP Architecture Exploration for Efficient Ipsec Encryption: A Case Study. [Citation Graph (0, 0)][DBLP]
    SCOPES, 2004, pp:33-46 [Conf]
  56. Oliver Wahlen, Manuel Hohenauer, Gunnar Braun, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, Xiaoning Nie
    Extraction of Efficient Instruction Schedulers from Cycle-True Processor Models. [Citation Graph (0, 0)][DBLP]
    SCOPES, 2003, pp:167-181 [Conf]
  57. Oliver Schliebusch, Andreas Hoffmann, Achim Nohl, Gunnar Braun, Heinrich Meyr
    Architecture Implementation Using the Machine Description Language LISA. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2002, pp:239-244 [Conf]
  58. Rudolf Mathar, Heinrich Meyr
    Stochastic modeling of the convergence behavior of concatenated codes. [Citation Graph (0, 0)][DBLP]
    VTC Fall (2), 2004, pp:1263-1265 [Conf]
  59. Oliver Wahlen, Manuel Hohenauer, Rainer Leupers, Heinrich Meyr
    Instruction Scheduler Generation for Retargetable Compilation. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2003, v:20, n:1, pp:34-41 [Journal]
  60. Gerhard Fettweis, Heinrich Meyr
    High-Rate Viterbi Processor: A Systolic Array Solution. [Citation Graph (0, 0)][DBLP]
    IEEE Journal on Selected Areas in Communications, 1990, v:8, n:8, pp:1520-1534 [Journal]
  61. Sebastian Ritz, Matthias Pankert, Vojin Zivojnovic, Heinrich Meyr
    High-Level Software Synthesis for the Design of Communication Systems. [Citation Graph (0, 0)][DBLP]
    IEEE Journal on Selected Areas in Communications, 1993, v:11, n:3, pp:348-358 [Journal]
  62. Herbert Dawid, Heinrich Meyr
    The Differential CORDIC Algorithm: Constant Scale Factor Redundant Implementation without Correcting Iterations. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1996, v:45, n:3, pp:307-318 [Journal]
  63. Gunnar Braun, Achim Nohl, Andreas Hoffmann, Oliver Schliebusch, Rainer Leupers, Heinrich Meyr
    A universal technique for fast and flexible instruction-set architecture simulation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:12, pp:1625-1639 [Journal]
  64. Andreas Hoffmann, Tim Kogel, Achim Nohl, Gunnar Braun, Oliver Schliebusch, Oliver Wahlen, Andreas Wieferink, Heinrich Meyr
    A novel methodology for the design of application-specificinstruction-set processors (ASIPs) using a machine description language. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2001, v:20, n:11, pp:1338-1354 [Journal]
  65. Stefan Pees, Andreas Hoffmann, Heinrich Meyr
    Retargetable compiled simulation of embedded processors using a machine description language. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2000, v:5, n:4, pp:815-834 [Journal]
  66. Lei Gao, Stefan Kraemer, Rainer Leupers, Gerd Ascheid, Heinrich Meyr
    A fast and generic hybrid simulation approach using C virtual machine. [Citation Graph (0, 0)][DBLP]
    CASES, 2007, pp:3-12 [Conf]
  67. Stefan Kraemer, Rainer Leupers, Gerd Ascheid, Heinrich Meyr
    Interactive presentation: SoftSIMD - exploiting subword parallelism using source code transformations. [Citation Graph (0, 0)][DBLP]
    DATE, 2007, pp:1349-1354 [Conf]
  68. Anupam Chattopadhyay, W. Ahmed, Kingshuk Karuri, David Kammler, Rainer Leupers, Gerd Ascheid, Heinrich Meyr
    Design space exploration of partially re-configurable embedded processors. [Citation Graph (0, 0)][DBLP]
    DATE, 2007, pp:319-324 [Conf]
  69. H. Ishebabi, Gerd Ascheid, Heinrich Meyr, O. Atak, A. Atalar, E. Arikan
    An efficient parallelization technique for high throughput FFT-ASIPs. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]
  70. Anupam Chattopadhyay, Z. Rakosi, Kingshuk Karuri, David Kammler, Rainer Leupers, Gerd Ascheid, Heinrich Meyr
    Pre- and Post-Fabrication Architecture Exploration for Partially Reconfigurable VLIW Processors. [Citation Graph (0, 0)][DBLP]
    IEEE International Workshop on Rapid System Prototyping, 2007, pp:189-194 [Conf]
  71. Hanno Scharwächter, David Kammler, Andreas Wieferink, Manuel Hohenauer, Kingshuk Karuri, Jianjiang Ceng, Rainer Leupers, Gerd Ascheid, Heinrich Meyr
    ASIP architecture exploration for efficient IPSec encryption: A case study. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Embedded Comput. Syst., 2007, v:6, n:2, pp:- [Journal]
  72. Herbert Dawid, Gerhard Fettweis, Heinrich Meyr
    A CMOS IC for Gb/s Viterbi decoding: system design and VLSI implementation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1996, v:4, n:1, pp:17-31 [Journal]
  73. Jianjiang Ceng, Weihua Sheng, Manuel Hohenauer, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, Gunnar Braun
    Modeling Instruction Semantics in ADL Processor Descriptions for C Compiler Retargeting. [Citation Graph (0, 0)][DBLP]
    VLSI Signal Processing, 2006, v:43, n:2-3, pp:235-246 [Journal]

  74. HySim: a fast simulation framework for embedded software development. [Citation Graph (, )][DBLP]


  75. A code-generator generator for multi-output instructions. [Citation Graph (, )][DBLP]


  76. A high-level virtual platform for early MPSoC software development. [Citation Graph (, )][DBLP]


  77. TotalProf: a fast and accurate retargetable source code profiler. [Citation Graph (, )][DBLP]


  78. MAPS: an integrated framework for MPSoC application parallelization. [Citation Graph (, )][DBLP]


  79. Multiprocessor performance estimation using hybrid simulation. [Citation Graph (, )][DBLP]


  80. Retargetable Code Optimization for Predicated Execution. [Citation Graph (, )][DBLP]


  81. High-level Modelling and Exploration of Coarse-grained Re-configurable Architectures. [Citation Graph (, )][DBLP]


  82. PCC: a modeling technique for mixed control/data flow systems. [Citation Graph (, )][DBLP]


  83. Trace-based KPN composability analysis for mapping simultaneous applications to MPSoC platforms. [Citation Graph (, )][DBLP]


  84. Asymptotic BER Analysis for MIMO-BICM with Zero-Forcing Detectors Assuming Imperfect CSI. [Citation Graph (, )][DBLP]


  85. Increasing data-bandwidth to instruction-set extensions through register clustering. [Citation Graph (, )][DBLP]


  86. A Generic Design Flow for Application Specific Processor Customization through Instruction-Set Extensions (ISEs). [Citation Graph (, )][DBLP]


  87. A Workbench for Analytical and Simulation Based Design Space Exploration of Software Defined Radios. [Citation Graph (, )][DBLP]


  88. Performance Evaluation of Opportunistic Beamforming with SINR Prediction for HSDPA. [Citation Graph (, )][DBLP]


  89. On the Influence of Pilot Symbol and Data Symbol Positioning on Turbo Synchronization. [Citation Graph (, )][DBLP]


  90. Long-Term Beamforming in Single Frequency Networks using Semidefinite Relaxation. [Citation Graph (, )][DBLP]


  91. Low-Complexity Channel-Adaptive MIMO Detection with Just-Acceptable Error Rate. [Citation Graph (, )][DBLP]


  92. Joint Reduction of Peak-to-Average Power Ratio and Out-of-Band Power in OFDM Systems. [Citation Graph (, )][DBLP]


  93. Searching in the Delta Lattice: An Efficient MIMO Detection for Iterative Receivers. [Citation Graph (, )][DBLP]


  94. Achievable Data Rate of Wideband OFDM With Data-Aided Channel Estimation. [Citation Graph (, )][DBLP]


  95. A Fast and Flexible Platform for Fault Injection and Evaluation in Verilog-Based Simulations. [Citation Graph (, )][DBLP]


  96. Efficient And Portable SDR Waveform Development: The Nucleus Concept [Citation Graph (, )][DBLP]


  97. A Scalable VLSI Architecture for Soft-Input Soft-Output Depth-First Sphere Decoding [Citation Graph (, )][DBLP]


  98. On Complexity, Energy- and Implementation-Efficiency of Channel Decoders [Citation Graph (, )][DBLP]


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