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Ryan Kastner: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Anup Hosangadi, Farzan Fallah, Ryan Kastner
    Common Subexpression Elimination Involving Multiple Variables for Linear DSP Synthesis. [Citation Graph (0, 0)][DBLP]
    ASAP, 2004, pp:202-212 [Conf]
  2. Anup Hosangadi, Farzan Fallah, Ryan Kastner
    Reducing hardware complexity of linear DSP systems by iteratively eliminating two-term common subexpressions. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2005, pp:523-528 [Conf]
  3. Philip Brisk, Adam Kaplan, Ryan Kastner, Majid Sarrafzadeh
    Instruction generation and regularity extraction for reconfigurable processors. [Citation Graph (0, 0)][DBLP]
    CASES, 2002, pp:262-269 [Conf]
  4. Elaheh Bozorgzadeh, Ryan Kastner, Majid Sarrafzadeh
    Creating and Exploiting Flexibility in Steiner Trees. [Citation Graph (0, 0)][DBLP]
    DAC, 2001, pp:195-198 [Conf]
  5. Adam Kaplan, Philip Brisk, Ryan Kastner
    Data communication estimation and reduction for reconfigurable systems. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:616-621 [Conf]
  6. Yan Meng, Andrew P. Brown, Ronald A. Iltis, Timothy Sherwood, Hua Lee, Ryan Kastner
    MP core: algorithm and design techniques for efficient channel estimation in wireless applications. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:297-302 [Conf]
  7. Yan Meng, Timothy Sherwood, Ryan Kastner
    Leakage power reduction of embedded memories on FPGAs through location assignment. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:612-617 [Conf]
  8. Gang Wang, Wenrui Gong, Brian DeRenzi, Ryan Kastner
    Design space exploration using time and resource duality with the ant colony optimization. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:451-454 [Conf]
  9. Anup Hosangadi, Farzan Fallah, Ryan Kastner
    Optimizing high speed arithmetic circuits using three-term extraction. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:1294-1299 [Conf]
  10. Ryan Kastner, Wenrui Gong, Xin Hao, Forrest Brewer, Adam Kaplan, Philip Brisk, Majid Sarrafzadeh
    Layout driven data communication optimization for high level synthesis. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:1185-1190 [Conf]
  11. Wenrui Gong, Yan Meng, Gang Wang, Ryan Kastner, Timothy Sherwood
    Data Partitioning and Optimizations for Reconfigurable Architectures. [Citation Graph (0, 0)][DBLP]
    ERSA, 2005, pp:239-242 [Conf]
  12. Wenrui Gong, Gang Wang, Ryan Kastner
    A High Performance Application Representation for Reconfigurable Systems. [Citation Graph (0, 0)][DBLP]
    ERSA, 2004, pp:218-224 [Conf]
  13. Ted Huffmire, Shreyas Prasad, Timothy Sherwood, Ryan Kastner
    Policy-Driven Memory Protection for Reconfigurable Hardware. [Citation Graph (0, 0)][DBLP]
    ESORICS, 2006, pp:461-478 [Conf]
  14. Kia Bazargan, Ryan Kastner, Seda Ogrenci, Majid Sarrafzadeh
    A C to Hardware/Software Compiler. [Citation Graph (0, 0)][DBLP]
    FCCM, 2000, pp:331-332 [Conf]
  15. Gang Wang, Wenrui Gong, Ryan Kastner
    Defect-Tolerant Nanocomputing Using Bloom Filters. [Citation Graph (0, 0)][DBLP]
    FCCM, 2006, pp:277-278 [Conf]
  16. Shahnam Mirzaei, Anup Hosangadi, Ryan Kastner
    High speed FIR filter implementation using add and shift method. [Citation Graph (0, 0)][DBLP]
    FPGA, 2006, pp:231- [Conf]
  17. Satish Sivaswamy, Gang Wang, Cristinel Ababei, Kia Bazargan, Ryan Kastner, Eli Bozorgzadeh
    HARP: hard-wired routing pattern FPGAs. [Citation Graph (0, 0)][DBLP]
    FPGA, 2005, pp:21-29 [Conf]
  18. Gang Wang, Wenrui Gong, Ryan Kastner
    Instruction scheduling using MAX-MIN ant system optimization. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2005, pp:44-49 [Conf]
  19. Yan Meng, Timothy Sherwood, Ryan Kastner
    On the Limits of Leakage Power Reduction in Caches. [Citation Graph (0, 0)][DBLP]
    HPCA, 2005, pp:154-165 [Conf]
  20. Wenrui Gong, Gang Wang, Ryan Kastner
    Storage assignment during high-level synthesis for configurable architectures. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2005, pp:3-6 [Conf]
  21. Anup Hosangadi, Farzan Fallah, Ryan Kastner
    Factoring and eliminating common subexpressions in polynomial expressions. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2004, pp:169-174 [Conf]
  22. Ryan Kastner, Elaheh Bozorgzadeh, Majid Sarrafzadeh
    Predictable Routing. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2000, pp:110-113 [Conf]
  23. Ryan Kastner, Seda Ogrenci Memik, Elaheh Bozorgzadeh, Majid Sarrafzadeh
    Instruction Generation for Hybrid Reconfigurable Systems. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2001, pp:127-0 [Conf]
  24. Seda Ogrenci Memik, Elaheh Bozorgzadeh, Ryan Kastner, Majid Sarrafzadeh
    A Super-Scheduler for Embedded Reconfigurable Systems. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2001, pp:391-0 [Conf]
  25. Ankur Srivastava, Ryan Kastner, Majid Sarrafzadeh
    Timing Driven Gate Duplication: Complexity Issues and Algorithms. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2000, pp:447-450 [Conf]
  26. Xiaojian Yang, Ryan Kastner, Majid Sarrafzadeh
    Congestion Reduction During Placement Based on Integer Programming. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2001, pp:573-576 [Conf]
  27. Gang Wang, Wenrui Gong, Ryan Kastner
    On the use of Bloom filters for defect maps in nanocomputing. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2006, pp:743-746 [Conf]
  28. Ryan Kastner, Elaheh Bozorgzadeh, Majid Sarrafzadeh
    An exact algorithm for coupling-free routing. [Citation Graph (0, 0)][DBLP]
    ISPD, 2001, pp:10-15 [Conf]
  29. Majid Sarrafzadeh, Elaheh Bozorgzadeh, Ryan Kastner, Ankur Srivastava
    Design and analysis of physical design algorithms. [Citation Graph (0, 0)][DBLP]
    ISPD, 2001, pp:82-89 [Conf]
  30. Xiaojian Yang, Ryan Kastner, Majid Sarrafzadeh
    Congestion estimation during top-down placement. [Citation Graph (0, 0)][DBLP]
    ISPD, 2001, pp:164-169 [Conf]
  31. Kia Bazargan, Ryan Kastner, Majid Sarrafzadeh
    3-D Floorplanning: Simulated Annealing and Greedy Placement Methods for Reconfigurable Computing Systems. [Citation Graph (0, 0)][DBLP]
    IEEE International Workshop on Rapid System Prototyping, 1999, pp:38-0 [Conf]
  32. Ted Huffmire, Brett Brotherton, Gang Wang, Timothy Sherwood, Ryan Kastner, Timothy E. Levin, Thuy D. Nguyen, Cynthia E. Irvine
    Moats and Drawbridges: An Isolation Primitive for Reconfigurable Hardware Based Systems. [Citation Graph (0, 0)][DBLP]
    IEEE Symposium on Security and Privacy, 2007, pp:281-295 [Conf]
  33. Anup Hosangadi, Farzan Fallah, Ryan Kastner
    Energy Efficient Hardware Synthesis of Polynomial Expressions. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2005, pp:653-658 [Conf]
  34. Ryan Kastner, Christina Hsieh, Miodrag Potkonjak, Majid Sarrafzadeh
    On the Sensitivity of Incremental Algorithms for Combinatorial Auctions. [Citation Graph (0, 0)][DBLP]
    WECWIS, 2002, pp:81-88 [Conf]
  35. Kia Bazargan, Ryan Kastner, Majid Sarrafzadeh
    Fast Template Placement for Reconfigurable Computing Systems. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2000, v:17, n:1, pp:68-83 [Journal]
  36. Yan Meng, Timothy Sherwood, Ryan Kastner
    Exploring the limits of leakage power reduction in caches. [Citation Graph (0, 0)][DBLP]
    TACO, 2005, v:2, n:3, pp:221-246 [Journal]
  37. Elaheh Bozorgzadeh, Ryan Kastner, Majid Sarrafzadeh
    Creating and exploiting flexibility in rectilinear Steiner trees. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:5, pp:605-615 [Journal]
  38. Anup Hosangadi, Farzan Fallah, Ryan Kastner
    Optimizing Polynomial Expressions by Algebraic Factorization and Common Subexpression Elimination. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:10, pp:2012-2022 [Journal]
  39. Ryan Kastner, Elaheh Bozorgzadeh, Majid Sarrafzadeh
    Pattern routing: use and theory for increasing predictability andavoiding coupling. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2002, v:21, n:7, pp:777-790 [Journal]
  40. Ankur Srivastava, Ryan Kastner, Majid Sarrafzadeh
    On the complexity of gate duplication. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2001, v:20, n:9, pp:1170-1176 [Journal]
  41. Gang Wang, Satish Sivaswamy, Cristinel Ababei, Kia Bazargan, Ryan Kastner, Elaheh Bozorgzadeh
    Statistical Analysis and Design of HARP FPGAs. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:10, pp:2088-2102 [Journal]
  42. Xiaojian Yang, Ryan Kastner, Majid Sarrafzadeh
    Congestion estimation during top-down placement. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2002, v:21, n:1, pp:72-80 [Journal]
  43. Ryan Kastner, Adam Kaplan, Seda Ogrenci Memik, Elaheh Bozorgzadeh
    Instruction generation for hybrid reconfigurable systems. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2002, v:7, n:4, pp:605-627 [Journal]
  44. Seda Ogrenci Memik, Ryan Kastner, Elaheh Bozorgzadeh, Majid Sarrafzadeh
    A scheduling algorithm for optimization and early planning in high-level synthesis. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2005, v:10, n:1, pp:33-57 [Journal]
  45. Xiaojian Yang, Maogang Wang, Ryan Kastner, Soheil Ghiasi, Majid Sarrafzadeh
    Congestion reduction during placement with provably good approximation bound. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2003, v:8, n:3, pp:316-333 [Journal]
  46. Ankur Srivastava, Ryan Kastner, Chunhong Chen, Majid Sarrafzadeh
    Timing driven gate duplication. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2004, v:12, n:1, pp:42-51 [Journal]
  47. Ronald A. Iltis, Shahnam Mirzaei, Ryan Kastner, Richard E. Cagley, Brad T. Weals
    Carrier Offset and Channel Estimation for Cooperative MIMO Sensor Networks. [Citation Graph (0, 0)][DBLP]
    GLOBECOM, 2006, pp:- [Conf]
  48. Gang Wang, Wenrui Gong, Brian DeRenzi, Ryan Kastner
    Exploring time/resource trade-offs by solving dual scheduling problems with the ant colony optimization. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2007, v:12, n:4, pp:- [Journal]
  49. Yan Meng, Wenrui Gong, Ryan Kastner, Timothy Sherwood
    Algorithm/Architecture Co-exploration for Designing Energy Efficient Wireless Channel Estimator. [Citation Graph (0, 0)][DBLP]
    J. Low Power Electronics, 2005, v:1, n:3, pp:238-248 [Journal]

  50. Design space exploration of a cooperative MIMO receiver for reconfigurable architectures. [Citation Graph (, )][DBLP]


  51. Parallelized Architecture of Multiple Classifiers for Face Detection. [Citation Graph (, )][DBLP]


  52. Xquasher: a tool for efficient computation of multiple linear expressions. [Citation Graph (, )][DBLP]


  53. Theoretical analysis of gate level information flow tracking. [Citation Graph (, )][DBLP]


  54. Threats and Challenges in Reconfigurable Hardware Security. [Citation Graph (, )][DBLP]


  55. Bit Error Rate, Power and Area Analysis of Multiple FPGA Implementations of Underwater FSK. [Citation Graph (, )][DBLP]


  56. Fpga-based face detection system using Haar classifiers. [Citation Graph (, )][DBLP]


  57. Combining static and dynamic defect-tolerance techniques for nanoscale memory systems. [Citation Graph (, )][DBLP]


  58. FPGA Implementation of High Speed FIR Filters Using Add and Shift Method. [Citation Graph (, )][DBLP]


  59. Energy benefits of reconfigurable hardware for use in underwater sensor nets. [Citation Graph (, )][DBLP]


  60. Design of a low-cost acoustic modem for moored oceanographic applications. [Citation Graph (, )][DBLP]


  61. Survey of hardware platforms for an energy efficient implementation of matching pursuits algorithm for shallow water networks. [Citation Graph (, )][DBLP]


  62. Hardware Implementation of Symbol Synchronization for Underwater FSK. [Citation Graph (, )][DBLP]


  63. Channel Equalization Based on Data Reuse LMS Algorithm for Shallow Water Acoustic Communication. [Citation Graph (, )][DBLP]


  64. Trustworthy System Security through 3-D Integrated Hardware. [Citation Graph (, )][DBLP]


  65. An FPGA Design Space Exploration Tool for Matrix Inversion Architectures. [Citation Graph (, )][DBLP]


  66. Hardware acceleration of multi-view face detection. [Citation Graph (, )][DBLP]


  67. Architectural optimization of decomposition algorithms for wireless communication systems. [Citation Graph (, )][DBLP]


  68. Enforcing memory policy specifications in reconfigurable hardware. [Citation Graph (, )][DBLP]


  69. Managing Security in FPGA-Based Embedded Systems. [Citation Graph (, )][DBLP]


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