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John V. McCanny: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Friederich Kupzog, Holger Blume, Tobias G. Noll, Kieran McLaughlin, Sakir Sezer, John McCanny
    Design and Analysis of Matching Circuit Architectures for a Closest Match Lookup. [Citation Graph (0, 0)][DBLP]
    AICT/ICIW, 2006, pp:56- [Conf]
  2. Colin C. W. Hui, Tiong Jiu Ding, John V. McCanny, Roger F. Woods
    A New FFT Architecture and Chip Design for Motion Compensation based on Phase Correlation. [Citation Graph (0, 0)][DBLP]
    ASAP, 1996, pp:83-92 [Conf]
  3. Zhaohui Liu, Kevin Dickson, John V. McCanny
    A floating-point CORDIC based SVD processor. [Citation Graph (0, 0)][DBLP]
    ASAP, 2003, pp:194-203 [Conf]
  4. John V. McCanny, Roger F. Woods, John G. McWhirter
    From Bit Level Systolic Arrays to HDTV Processor Chips. [Citation Graph (0, 0)][DBLP]
    ASAP, 2006, pp:159-162 [Conf]
  5. Neil Smyth, Máire McLoone, John V. McCanny
    An Adaptable And Scalable Asymmetric Cryptographic Processor. [Citation Graph (0, 0)][DBLP]
    ASAP, 2006, pp:341-346 [Conf]
  6. Swee Yeow, John V. McCanny
    A VLSI Architecture for Advanced Video Coding Motion Estimation. [Citation Graph (0, 0)][DBLP]
    ASAP, 2003, pp:293-0 [Conf]
  7. John V. McCanny
    On the use of most significant digit first arithmetic in the design of high performance DSP chips. [Citation Graph (0, 0)][DBLP]
    Algorithms and Parallel VLSI Architectures, 1991, pp:243-260 [Conf]
  8. Máire McLoone, John V. McCanny
    High Performance Single-Chip FPGA Rijndael Algorithm Implementations. [Citation Graph (0, 0)][DBLP]
    CHES, 2001, pp:65-76 [Conf]
  9. Ciaran McIvor, Máire McLoone, John V. McCanny
    FPGA Montgomery Multiplier Architectures - A Comparison. [Citation Graph (0, 0)][DBLP]
    FCCM, 2004, pp:279-282 [Conf]
  10. Máire McLoone, John V. McCanny
    Single-Chip FPGA Implementation of the Advanced Encryption Standard Algorithm. [Citation Graph (0, 0)][DBLP]
    FPL, 2001, pp:152-161 [Conf]
  11. Máire McLoone, John V. McCanny
    Very High Speed 17 Gbps SHACAL Encryption Architecture. [Citation Graph (0, 0)][DBLP]
    FPL, 2003, pp:111-120 [Conf]
  12. Ciaran McIvor, Máire McLoone, John V. McCanny
    High-Radix Systolic Modular Multiplication on Reconfigurable Hardware. [Citation Graph (0, 0)][DBLP]
    FPT, 2005, pp:13-18 [Conf]
  13. Paul McCanny, Shahid Masud, John V. McCanny
    An efficient architecture for the 2-D biorthogonal discrete wavelet transform. [Citation Graph (0, 0)][DBLP]
    ICIP (3), 2001, pp:314-317 [Conf]
  14. Kieran McLaughlin, Friederich Kupzog, Holger Blume, Sakir Sezer, Tobias G. Noll, John McCanny
    Design and analysis of matching circuit architectures for a closest match lookup. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2006, pp:- [Conf]
  15. Ciaran McIvor, Máire McLoone, John V. McCanny
    A high-speed, low latency RSA decryption silicon core. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2003, pp:133-136 [Conf]
  16. Ciaran McIvor, Máire McLoone, John V. McCanny
    FPGA Montgomery modular multiplication architectures suitable for ECCs over GF(p). [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2004, pp:509-512 [Conf]
  17. Shahid Masud, John V. McCanny
    Rapid Design of Discrete Orthonormal Wavelet Transforms. [Citation Graph (0, 0)][DBLP]
    International Workshop on Rapid System Prototyping, 1998, pp:142-0 [Conf]
  18. O. C. McNally, John V. McCanny, Roger F. Woods
    Design of a Highly Pipelined 2nd Order IIR Filter Chip. [Citation Graph (0, 0)][DBLP]
    VLSI, 1991, pp:19-28 [Conf]
  19. Stephen E. McQuillan, John V. McCanny
    A Systematic Methodology for the Design of High Performance Recursive Digital Filters. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1995, v:44, n:8, pp:971-982 [Journal]

  20. New algorithms and VLSI architectures for SRT division and square root. [Citation Graph (, )][DBLP]


  21. Reconfigurable Motion Estimation Architecture for Multi-standard Video Compression. [Citation Graph (, )][DBLP]


  22. Differential Power Analysis of a SHACAL-2 hardware implementation. [Citation Graph (, )][DBLP]


  23. Systolic Array Based Architecture for Variable Block-Size Motion Estimation. [Citation Graph (, )][DBLP]


  24. Novel Content Addressable Memory Architecture for Adaptive Systems. [Citation Graph (, )][DBLP]


  25. High performance IP lookup circuit using DDR SDRAM. [Citation Graph (, )][DBLP]


  26. Multi-standard sub-pixel interpolation architecture for video Motion Estimation. [Citation Graph (, )][DBLP]


  27. Reduced-complexity MSGR-based matrix inversion. [Citation Graph (, )][DBLP]


  28. Is the differential frequency-based attack effective against random delay insertion? [Citation Graph (, )][DBLP]


  29. Modified givens rotations and their application to matrix inversion. [Citation Graph (, )][DBLP]


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