The SCEAS System
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## Search the dblp DataBase
John V. McCanny:
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## Publications of Author- Friederich Kupzog, Holger Blume, Tobias G. Noll, Kieran McLaughlin, Sakir Sezer, John McCanny
**Design and Analysis of Matching Circuit Architectures for a Closest Match Lookup.**[Citation Graph (0, 0)][DBLP] AICT/ICIW, 2006, pp:56- [Conf] - Colin C. W. Hui, Tiong Jiu Ding, John V. McCanny, Roger F. Woods
**A New FFT Architecture and Chip Design for Motion Compensation based on Phase Correlation.**[Citation Graph (0, 0)][DBLP] ASAP, 1996, pp:83-92 [Conf] - Zhaohui Liu, Kevin Dickson, John V. McCanny
**A floating-point CORDIC based SVD processor.**[Citation Graph (0, 0)][DBLP] ASAP, 2003, pp:194-203 [Conf] - John V. McCanny, Roger F. Woods, John G. McWhirter
**From Bit Level Systolic Arrays to HDTV Processor Chips.**[Citation Graph (0, 0)][DBLP] ASAP, 2006, pp:159-162 [Conf] - Neil Smyth, Máire McLoone, John V. McCanny
**An Adaptable And Scalable Asymmetric Cryptographic Processor.**[Citation Graph (0, 0)][DBLP] ASAP, 2006, pp:341-346 [Conf] - Swee Yeow, John V. McCanny
**A VLSI Architecture for Advanced Video Coding Motion Estimation.**[Citation Graph (0, 0)][DBLP] ASAP, 2003, pp:293-0 [Conf] - John V. McCanny
**On the use of most significant digit first arithmetic in the design of high performance DSP chips.**[Citation Graph (0, 0)][DBLP] Algorithms and Parallel VLSI Architectures, 1991, pp:243-260 [Conf] - Máire McLoone, John V. McCanny
**High Performance Single-Chip FPGA Rijndael Algorithm Implementations.**[Citation Graph (0, 0)][DBLP] CHES, 2001, pp:65-76 [Conf] - Ciaran McIvor, Máire McLoone, John V. McCanny
**FPGA Montgomery Multiplier Architectures - A Comparison.**[Citation Graph (0, 0)][DBLP] FCCM, 2004, pp:279-282 [Conf] - Máire McLoone, John V. McCanny
**Single-Chip FPGA Implementation of the Advanced Encryption Standard Algorithm.**[Citation Graph (0, 0)][DBLP] FPL, 2001, pp:152-161 [Conf] - Máire McLoone, John V. McCanny
**Very High Speed 17 Gbps SHACAL Encryption Architecture.**[Citation Graph (0, 0)][DBLP] FPL, 2003, pp:111-120 [Conf] - Ciaran McIvor, Máire McLoone, John V. McCanny
**High-Radix Systolic Modular Multiplication on Reconfigurable Hardware.**[Citation Graph (0, 0)][DBLP] FPT, 2005, pp:13-18 [Conf] - Paul McCanny, Shahid Masud, John V. McCanny
**An efficient architecture for the 2-D biorthogonal discrete wavelet transform.**[Citation Graph (0, 0)][DBLP] ICIP (3), 2001, pp:314-317 [Conf] - Kieran McLaughlin, Friederich Kupzog, Holger Blume, Sakir Sezer, Tobias G. Noll, John McCanny
**Design and analysis of matching circuit architectures for a closest match lookup.**[Citation Graph (0, 0)][DBLP] IPDPS, 2006, pp:- [Conf] - Ciaran McIvor, Máire McLoone, John V. McCanny
**A high-speed, low latency RSA decryption silicon core.**[Citation Graph (0, 0)][DBLP] ISCAS (4), 2003, pp:133-136 [Conf] - Ciaran McIvor, Máire McLoone, John V. McCanny
**FPGA Montgomery modular multiplication architectures suitable for ECCs over GF(p).**[Citation Graph (0, 0)][DBLP] ISCAS (3), 2004, pp:509-512 [Conf] - Shahid Masud, John V. McCanny
**Rapid Design of Discrete Orthonormal Wavelet Transforms.**[Citation Graph (0, 0)][DBLP] International Workshop on Rapid System Prototyping, 1998, pp:142-0 [Conf] - O. C. McNally, John V. McCanny, Roger F. Woods
**Design of a Highly Pipelined 2nd Order IIR Filter Chip.**[Citation Graph (0, 0)][DBLP] VLSI, 1991, pp:19-28 [Conf] - Stephen E. McQuillan, John V. McCanny
**A Systematic Methodology for the Design of High Performance Recursive Digital Filters.**[Citation Graph (0, 0)][DBLP] IEEE Trans. Computers, 1995, v:44, n:8, pp:971-982 [Journal] **New algorithms and VLSI architectures for SRT division and square root.**[Citation Graph (, )][DBLP]**Reconfigurable Motion Estimation Architecture for Multi-standard Video Compression.**[Citation Graph (, )][DBLP]**Differential Power Analysis of a SHACAL-2 hardware implementation.**[Citation Graph (, )][DBLP]**Systolic Array Based Architecture for Variable Block-Size Motion Estimation.**[Citation Graph (, )][DBLP]**Novel Content Addressable Memory Architecture for Adaptive Systems.**[Citation Graph (, )][DBLP]**High performance IP lookup circuit using DDR SDRAM.**[Citation Graph (, )][DBLP]**Multi-standard sub-pixel interpolation architecture for video Motion Estimation.**[Citation Graph (, )][DBLP]**Reduced-complexity MSGR-based matrix inversion.**[Citation Graph (, )][DBLP]**Is the differential frequency-based attack effective against random delay insertion?**[Citation Graph (, )][DBLP]**Modified givens rotations and their application to matrix inversion.**[Citation Graph (, )][DBLP]
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