Search the dblp DataBase

Publications of Author

1. Tuomas Järvinen, Perttu Salmela, Harri Sorokin, Jarmo Takala
   Stride Permutation Networks for Array Processors. [Citation Graph (0, 0)][DBLP]
   ASAP, 2004, pp:376-386 [Conf]
   
2. Perttu Salmela, Tuomas Järvinen, Teemu Sipilä, Jarmo Takala
   256-State Rate 1/2 Viterbi Decoder on TTA Processor. [Citation Graph (0, 0)][DBLP]
   ASAP, 2005, pp:370-378 [Conf]
   
3. Jarmo Takala, Tuomas Järvinen, Harri Sorokin
   Conflict-free parallel memory access scheme for FFT processors. [Citation Graph (0, 0)][DBLP]
   ISCAS (4), 2003, pp:524-527 [Conf]
   
4. T. S. Jarvinen, J. H. Takala, David Akopian, J. P. P. Saarinen
   Register-based multi-port perfect shuffle networks. [Citation Graph (0, 0)][DBLP]
   ISCAS (4), 2001, pp:306-309 [Conf]
   
5. J. H. Takala, T. S. Jarvinen, J. A. Nikara
   Register-based reordering networks for matrix transpose. [Citation Graph (0, 0)][DBLP]
   ISCAS (4), 2002, pp:874-877 [Conf]
   
6. Tuomas Järvinen, Jarmo Takala
   Register-Based Permutation Networks for Stride Permutations. [Citation Graph (0, 0)][DBLP]
   SAMOS, 2004, pp:108-117 [Conf]
   
7. Perttu Salmela, Pekka Jääskeläinen, Tuomas Järvinen, Jarmo Takala
   Software Pipelining Support for Transport Triggered Architecture Processors. [Citation Graph (0, 0)][DBLP]
   SAMOS, 2006, pp:237-247 [Conf]
   
8. Tuomas Järvinen, Perttu Salmela, Teemu Sipilä, Jarmo Takala
   In-Place Storage of Path Metrics in Viterbi Decoders. [Citation Graph (0, 0)][DBLP]
   VLSI-SOC, 2003, pp:295-300 [Conf]
   
9. Tuomas Järvinen, Perttu Salmela, Teemu Sipilä, Jarmo Takala
   Systematic approach for path metric access in Viterbi decoders. [Citation Graph (0, 0)][DBLP]
   IEEE Transactions on Communications, 2005, v:53, n:5, pp:755-759 [Journal]
   
10. Tuomas Järvinen, Perttu Salmela, Konsta Punkka, Jarmo Takala
    Evaluation of stride permutation networks. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]