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Pieter van der Wolf: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Bart Kienhuis, Ed F. Deprettere, Kees A. Vissers, Pieter van der Wolf
    An Approach for Quantitative Analysis of Application-Specific Dataflow Architectures. [Citation Graph (0, 0)][DBLP]
    ASAP, 1997, pp:338-349 [Conf]
  2. Pieter van der Wolf, W. M. Kruijtzer, Jos T. J. van Eijndhoven
    T2: System-Level Design of Embedded Media Systems. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2002, pp:14-15 [Conf]
  3. Tomas Henriksson, Jeffrey Kang, Pieter van der Wolf
    Implementation of dynamic streaming Applications on heterogeneous multi-Processor architectures. [Citation Graph (0, 0)][DBLP]
    CODES+ISSS, 2005, pp:57-62 [Conf]
  4. Paul Lieverse, Pieter van der Wolf, Ed F. Deprettere
    A trace transformation technique for communication refinement. [Citation Graph (0, 0)][DBLP]
    CODES, 2001, pp:134-139 [Conf]
  5. Bart Kienhuis, Ed F. Deprettere, Kees A. Vissers, Pieter van der Wolf
    The construction of a retargetable simulator for an architecture template. [Citation Graph (0, 0)][DBLP]
    CODES, 1998, pp:125-129 [Conf]
  6. Pieter van der Wolf, Erwin A. de Kock, Tomas Henriksson, Wido Kruijtzer, Gerben Essink
    Design and programming of embedded multiprocessors: an interface-centric approach. [Citation Graph (0, 0)][DBLP]
    CODES+ISSS, 2004, pp:206-217 [Conf]
  7. Pieter van der Wolf, Paul Lieverse, Mudit Goel, David La Hei, Kees A. Vissers
    An MPEG-2 decoder case study as a driver for a system level design methodology. [Citation Graph (0, 0)][DBLP]
    CODES, 1999, pp:33-37 [Conf]
  8. K. Olav ten Bosch, Peter Bingley, Pieter van der Wolf
    Design Flow Management in the NELSIS CAD Framework. [Citation Graph (0, 0)][DBLP]
    DAC, 1991, pp:711-716 [Conf]
  9. Erwin A. de Kock, W. J. M. Smits, Pieter van der Wolf, Jean-Yves Brunel, W. M. Kruijtzer, Paul Lieverse, Kees A. Vissers, Gerben Essink
    YAPI: application modeling for signal processing systems. [Citation Graph (0, 0)][DBLP]
    DAC, 2000, pp:402-405 [Conf]
  10. Ing Widya, T. G. R. van Leuken, Pieter van der Wolf
    Concurrency Control in a VLSI Design Database. [Citation Graph (0, 0)][DBLP]
    DAC, 1988, pp:357-362 [Conf]
  11. Pieter van der Wolf, T. G. R. van Leuken
    Object Type Oriented Data Modeling for VLSI Data Management. [Citation Graph (0, 0)][DBLP]
    DAC, 1988, pp:351-356 [Conf]
  12. Pieter van der Wolf, G. W. Sloof, Peter Bingley, Patrick Dewilde
    Meta Data Management in the NELSIS CAD Framework. [Citation Graph (0, 0)][DBLP]
    DAC, 1990, pp:142-149 [Conf]
  13. Vladimir D. Zivkovic, Erwin A. de Kock, Pieter van der Wolf, Ed F. Deprettere
    Fast and Accurate Multiprocessor Architecture Exploration with Symbolic Programs. [Citation Graph (0, 0)][DBLP]
    DATE, 2003, pp:10656-10661 [Conf]
  14. Jeffrey Kang, Tomas Henriksson, Pieter van der Wolf
    An Interface for the Design and Implementation of Dynamic Applications on Multi-Processor Architectures. [Citation Graph (0, 0)][DBLP]
    ESTImedia, 2005, pp:101-106 [Conf]
  15. Peter Bingley, K. Olav ten Bosch, Pieter van der Wolf
    Incorporating design flow management in a framework based CAD system. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1992, pp:538-545 [Conf]
  16. K. Olav ten Bosch, Pieter van der Wolf, Peter Bingley
    A flow-based user interface for efficient execution of the design cycle. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1993, pp:356-363 [Conf]
  17. Rolf Ernst, Kees A. Vissers, Pieter van der Wolf, Gert-Jan van Rootselaar
    System level design and debug of high-performance embedded media systems (tutorial). [Citation Graph (0, 0)][DBLP]
    ICCAD, 1999, pp:461- [Conf]
  18. Paul Lieverse, Todor Stefanov, Pieter van der Wolf, Ed F. Deprettere
    System Level Design with Spade: an M-JPEG Case Study. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2001, pp:31-38 [Conf]
  19. Pieter van der Wolf, K. Olav ten Bosch, Alfred van der Hoeven
    An enhanced flow model for constraint handling in hierarchical multi-view design environments. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1994, pp:500-507 [Conf]
  20. Jos T. J. van Eijndhoven, Kees A. Vissers, Evert-Jan D. Pol, P. Struik, R. H. J. Bloks, Pieter van der Wolf, Harald P. E. Vranken, Frans Sijstermans, M. J. A. Tromp, Andy D. Pimentel
    TriMedia CPU64 Architecture. [Citation Graph (0, 0)][DBLP]
    ICCD, 1999, pp:586-592 [Conf]
  21. Evert-Jan D. Pol, Bas Aarts, Jos T. J. van Eijndhoven, P. Struik, Pieter van der Wolf, Frans Sijstermans, M. J. A. Tromp, Jan-Willem van de Waerdt
    TriMedia CPU64 Application Development Environment. [Citation Graph (0, 0)][DBLP]
    ICCD, 1999, pp:593-598 [Conf]
  22. Martijn J. Rutten, Jos T. J. van Eijndhoven, Evert-Jan D. Pol, Egbert G. T. Jaspers, Pieter van der Wolf, Om Prakash Gangwal, Adwin H. Timmer
    Eclipse: Heterogeneous Multiprocessor Architecture for Flexible Media Processing. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2002, pp:- [Conf]
  23. Bart Kienhuis, Ed F. Deprettere, Pieter van der Wolf, Kees A. Vissers
    A Methodology to Design Programmable Embedded Systems - The Y-Chart Approach. [Citation Graph (0, 0)][DBLP]
    Embedded Processor Design Challenges, 2002, pp:18-37 [Conf]
  24. Pieter van der Wolf, W. M. Kruijtzer, Jos T. J. van Eijndhoven
    System-Level Design of Embedded Media Systems (Tutorial Abstract). [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2002, pp:14-15 [Conf]
  25. Andy D. Pimentel, Louis O. Hertzberger, Paul Lieverse, Pieter van der Wolf, Ed F. Deprettere
    Exploring Embedded-Systems Architectures with Artemis. [Citation Graph (0, 0)][DBLP]
    IEEE Computer, 2001, v:34, n:11, pp:57-63 [Journal]
  26. Martijn J. Rutten, Jos T. J. van Eijndhoven, Egbert G. T. Jaspers, Pieter van der Wolf, Evert-Jan D. Pol, Om Prakash Gangwal, Adwin H. Timmer
    A Heterogeneous Multiprocessor Architecture for Flexible Media Processing. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2002, v:19, n:4, pp:39-50 [Journal]

  27. Video Processing Requirements on SoC Infrastructures. [Citation Graph (, )][DBLP]


  28. Performance Analysis of SoC Architectures Based on Latency-Rate Servers. [Citation Graph (, )][DBLP]


  29. Industrial IP Integration Flows based on IP-XACT Standards. [Citation Graph (, )][DBLP]


  30. Flow regulation for on-chip communication. [Citation Graph (, )][DBLP]


  31. Real-Time Analysis for Memory Access in Media Processing SoCs: A Practical Approach. [Citation Graph (, )][DBLP]


  32. Network Calculus Applied to Verification of Memory Access Performance in SoCs. [Citation Graph (, )][DBLP]


  33. TTL Hardware Interface: A High-Level Interface for Streaming Multiprocessor Architectures. [Citation Graph (, )][DBLP]


  34. A flexible access control mechanism for CAD frameworks. [Citation Graph (, )][DBLP]


  35. Design data management in a distributed hardware environment. [Citation Graph (, )][DBLP]


  36. On the architecture of a CAD framework: the NELSIS approach. [Citation Graph (, )][DBLP]


  37. Transparent Embedded Compression in Systems-on-Chip. [Citation Graph (, )][DBLP]


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