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Publications of Author

1. George Kornaros, Theofanis Orphanoudakis, Ioannis Papaefstathiou
   GFS: An Efficient Implementation of Fair Scheduling for Mult-Gigabit Packet Networks. [Citation Graph (0, 0)][DBLP]
   ASAP, 2003, pp:389-399 [Conf]
   
2. Ioannis Papaefstathiou, Theofanis Orphanoudakis, George Kornaros, Christopher Kachris, Ioannis Mavroidis, Aristides Nikologiannis
   Queue Management in Network Processors. [Citation Graph (0, 0)][DBLP]
   DATE, 2005, pp:112-117 [Conf]
   
3. George Kornaros, Theofanis Orphanoudakis, Nicholaos Zervos
   An Efficient Implementation of Fair Load Balancing over Multi-CPU SOC Architectures. [Citation Graph (0, 0)][DBLP]
   DSD, 2003, pp:197-205 [Conf]
   
4. George Kornaros, Theofanis Orphanoudakis, Yannis Papaefstathiou
   Active flow identifiers for scalable, QoS scheduling in 10-Gbps network processors. [Citation Graph (0, 0)][DBLP]
   ISCAS (2), 2003, pp:97-100 [Conf]
   
5. Ioannis Papaefstathiou, Helen-Catherine Leligou, Theofanis Orphanoudakis, George Kornaros, Nicholaos Zervos, George E. Konstantoulakis
   An innovative scheduling scheme for high-speed network processors. [Citation Graph (0, 0)][DBLP]
   ISCAS (2), 2003, pp:93-96 [Conf]
   
6. John D. Angelopoulos, N. Leligou, Theofanis Orphanoudakis, Giannis Pikrammenos, J. Sifnaios, Iakovos S. Venieris
   Access Control in Shared Access Networks Supporting Internet DiffServ. [Citation Graph (0, 0)][DBLP]
   ONDM, 2000, pp:235-246 [Conf]
   
7. Kyriakos Vlachos, Nikos A. Nikolaou, Theofanis Orphanoudakis, Stylianos Perissakis, Dionisios N. Pnevmatikatos, George Kornaros, J. A. Sanchez, George E. Konstantoulakis
   Processing and Scheduling Components in an Innovative Network Processor Architecture. [Citation Graph (0, 0)][DBLP]
   VLSI Design, 2003, pp:195-201 [Conf]
   
8. John Angelopoulos, Theofanis Orfanoudakis
   An ATM-friendly MAC for traffic concentration in HFC systems. [Citation Graph (0, 0)][DBLP]
   Computer Communications, 1998, v:21, n:6, pp:516-529 [Journal]
   
9. Ioannis Papaefstathiou, Stylianos Perissakis, Theofanis Orphanoudakis, Nikos A. Nikolaou, George Kornaros, Nicholas Zervos, George E. Konstantoulakis, Dionisios N. Pnevmatikatos, Kyriakos Vlachos
   PRO3: A Hybrid NPU Architecture. [Citation Graph (0, 0)][DBLP]
   IEEE Micro, 2004, v:24, n:5, pp:20-33 [Journal]
   
10. Theofanis Orphanoudakis, Stylianos Perissakis, Kostas Pramataris, Nikos A. Nikolaou, Nicholas Zervos, Matthias Steck, Christoph Baumhof, Diederik Verkest, Chantal Ykman-Couvreur, Gregory Doumenis, Fotis Karoubalis, Ioanna Theologitou, Dionisios I. Reisis, George E. Konstantoulakis, Nikos Vogiatzis
    Hardware Architectures for the Efficient Implementation of Multi-Service Broadband Access and Multimedia Home Networks. [Citation Graph (0, 0)][DBLP]
    Telecommunication Systems, 2003, v:23, n:3-4, pp:351-367 [Journal]
    
11. Helen-Catherine Leligou, Charalambos Linardakis, Konstantinos Kanonakis, John D. Angelopoulos, Theofanis Orphanoudakis
    Efficient medium arbitration of FSAN-compliant GPONs. [Citation Graph (0, 0)][DBLP]
    Int. J. Communication Systems, 2006, v:19, n:5, pp:603-617 [Journal]
    
12. Kyriakos Vlachos, Theofanis Orphanoudakis, Yannis Papaefstathiou, Nikos A. Nikolaou, Dionisios N. Pnevmatikatos, George E. Konstantoulakis, Jorge-A. Sanchez-P.
    Design and performance evaluation of a Programmable Packet Processing Engine (PPE) suitable for high-speed network processors units. [Citation Graph (0, 0)][DBLP]
    Microprocessors and Microsystems, 2007, v:31, n:3, pp:188-199 [Journal]
    
13. Ioannis Papaefstathiou, Theofanis Orphanoudakis, George Kornaros, Christopher Kachris, Ioannis Mavroidis, Aristides Nikologiannis
    Queue Management in Network Processors [Citation Graph (0, 0)][DBLP]
    CoRR, 2007, v:0, n:, pp:- [Journal]
    
14. 
    An Embedded Networking SoC for purely Ethernet MANs/WANs. [Citation Graph (, )][DBLP]
    
    
15. 
    An Efficient Optical Switch Architecture with Controlled Latency for GRID Networks. [Citation Graph (, )][DBLP]